Proceedings ArticleDOI
Study of LER/LWR induced V T variability of an EδDC n-channel MOS transistor
Sarmista Sengupta,Soumya Pandit +1 more
- pp 685-689
TLDR
In this article, a simple model to study the threshold voltage variability due to line edge roughness (LER) for an n-channel EδDC MOS transistor is presented.Abstract:
In this paper we present a simple model to study the threshold voltage variability due to line edge roughness (LER) for an n-channel EδDC MOS transistor. The concept of propagation of variance is utilized here. Impact of variation in rms amplitude and correlation length of edge fluctuation on threshold voltage variability is studied. The model is verified with calibrated technology computer aided design (TCAD) simulation results. Impact of channel engineering for reduction of LER induced threshold voltage variability is studied in detail.read more
References
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Journal ArticleDOI
Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness
TL;DR: In this paper, the impact of the gate line edge roughness (LER) on the intrinsic parameters fluctuations in deep decananometer (sub 50 nm) gate MOSFETs was investigated.
Journal ArticleDOI
Threshold voltage model for deep-submicrometer MOSFETs
TL;DR: In this article, the threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep submicrometer range has been investigated.
Journal ArticleDOI
Suppression of random dopant-induced threshold voltage fluctuations in sub-0.1-/spl mu/m MOSFET's with epitaxial and /spl delta/-doped channels
Asen Asenov,Subhash Saini +1 more
TL;DR: In this article, a detailed three-dimensional (3D) statistical "atomistic" simulation study of fluctuation-resistant sub 0.1/spl mu/m MOSFET architectures with epitaxial channels and delta doping is presented.
Proceedings ArticleDOI
Impact of additional factors in threshold voltage variability of metal/high-k gate stacks and its reduction by controlling crystalline structure and grain size in the metal gates
Kenji Ohmori,Takeo Matsuki,D. Ishikawa,Tetsu Morooka,T. Aminaka,Yoshihiro Sugita,Toyohiro Chikyow,Kenji Shiraishi,Yasuo Nara,Kizuku Yamada +9 more
TL;DR: In this article, the authors showed that the incorporation of C into TiN metal gates transforms the crystalline film into an amorphous one, effecting a reduction in the threshold voltage variability in HfSiON pFET devices.
Journal ArticleDOI
Gate Line Edge Roughness Model for Estimation of FinFET Performance Variability
TL;DR: In this paper, the impact of gate line edge roughness (LER) on the performance of double-gate FinFET devices is investigated using a framework that links device performance to commonly used LER descriptors, namely, correlation length, rms amplitude or standard deviation (sigma) of the line edge from its mean value, and roughness exponent ( alpha).