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Journal ArticleDOI

Subthreshold conduction in MOSFET's

G.W. Taylor
- 01 Mar 1978 - 
- Vol. 25, Iss: 3, pp 337-350
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TLDR
With the application of substrate bias, it is concluded from the data and the theory that two-dimensional effects can cause dramatic increases in the drain conductance to confirm the theory over a wide range of drain and gate voltages.
Abstract
The dependence of channel current in subthreshold operation upon drain, gate, and substrate voltages is formulated in terms of a simple model. The basic results are consistent with earlier approaches for long-channel devices. For short-channel devices, the variation of current with drain voltage up to the punch-through voltage is accurately described. The threshold voltage of a short-channel device as a function of applied voltages follows as a natural result of the derivation. Results are presented which confirm the theory over a wide range of drain and gate voltages. With the application of substrate bias it is concluded from the data and the theory that two-dimensional effects can cause dramatic increases in the drain conductance.

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Journal ArticleDOI

BSIM: Berkeley short-channel IGFET model for MOS transistors

TL;DR: The Berkeley short-channel IGFET model (BSIM) as discussed by the authors is an accurate and computationally efficient MOS transistor model, and its associated characterization facility for advanced integrated-circuit design is described.
Journal ArticleDOI

Threshold voltage model for deep-submicrometer MOSFETs

TL;DR: In this article, the threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep submicrometer range has been investigated.
Journal ArticleDOI

Modeling of transconductance degradation and extraction of threshold voltage in thin oxide MOSFET's

TL;DR: In this article, the authors modify the Pao-Sah drain current model to incorporate a mobility model and obtain 3% accuracy from subthreshold to very strong inversion for a wide range of substrate biases.
Journal ArticleDOI

VLSI limitations from drain-induced barrier lowering

TL;DR: In this paper, the important design parameters relating to Drain-Induced Barrier lowering (DIBL) are investigated using a numerical two-dimensional model, and a simple conceptual model is introduced as an aid for understanding the results.
Journal ArticleDOI

VLSI limitations from drain-induced barrier lowering

TL;DR: In this paper, the important design parameters relating to Drain-Induced Barrier lowering (DIBL) are investigated using a numerical two-dimensional model, and a simple conceptual model is introduced as an aid for understanding the results.
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