Journal ArticleDOI
When are transmission-line effects important for on-chip interconnections?
Alina Deutsch,Gerard V. Kopcsay,Phillip J. Restle,Howard H. Smith,George A. Katopis,Wiren D. Becker,Paul W. Coteus,C.W. Surovic,Barry J. Rubin,R.P. Dunne,T. Gallo,Keith A. Jenkins,L.M. Terman,Robert H. Dennard,George Anthony Sai-Halasz,Byron L. Krauter,D.R. Knebel +16 more
TLDR
In this paper, the authors analyzed short, medium, and long on-chip interconnections having linewidths of 0.45-52 /spl mu/m in a five-metal-layer structure.Abstract:
Short, medium, and long on-chip interconnections having linewidths of 0.45-52 /spl mu/m are analyzed in a five-metal-layer structure. We study capacitive coupling for short lines, inductive coupling for medium-length lines, inductance and resistance of the current return path in the power buses, and line resistive losses for the global wiring. Design guidelines and technology changes are proposed to achieve minimum delay and contain crosstalk for local and global wiring. Conditional expressions are given to determine when transmission-line effects are important for accurate delay and crosstalk prediction.read more
Citations
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Journal ArticleDOI
Rationale and challenges for optical interconnects to electronic chips
TL;DR: Optical interconnects to silicon CMOS chips are discussed in this paper, where various arguments for introducing optical interconnections to silicon chips are summarized, and the challenges for optical, optoelectronic, and integration technologies are discussed.
Journal ArticleDOI
Simulation of high-speed interconnects
Ramachandra Achar,Michel Nakhla +1 more
TL;DR: In this review paper various high-speed interconnect effects are briefly discussed, recent advances in transmission line macromodeling techniques are presented, and simulation of high- speed interconnects using model-reduction-based algorithms is discussed in detail.
Journal ArticleDOI
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
Yehea Ismail,Eby G. Friedman +1 more
TL;DR: The importance of inductance in high-performance very large scale integration (VLSI) design methodologies will increase as technologies scale, as the error between the RC and RLC models increases as the gate parasitic impedances decrease with technology scaling.
Journal ArticleDOI
A clock distribution network for microprocessors
Phillip J. Restle,Timothy G. McNamara,David A. Webber,Peter J. Camporese,K.F. Eng,Keith A. Jenkins,D.H. Allen,M.J. Rohn,M.P. Quaranta,David William Boerstler,Charles J. Alpert,C.A. Carter,R.N. Bailey,J.G. Petrovick,Byron L. Krauter,Bradley McCredie +15 more
TL;DR: A global clock distribution strategy implemented on several microprocessor chips is described, which consists of buffered, tunable tree networks, with the final trees all driving a common grid.
Proceedings ArticleDOI
Performance analysis of carbon nanotube interconnects for VLSI applications
TL;DR: It is shown that CNT bundles can outperform copper for long intermediate and global interconnects, and can be engineered to compete with copper for local level interConnects.
References
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Journal ArticleDOI
High-speed signal propagation on lossy transmission lines
Alina Deutsch,G.V. Kopcsay,Vincent Ranieri,J. Cataldo,Eileen A. Galligan,W. Graham,Richard P Mcgouey,Sharon L. Nunes,Jurij R. Paraszczak,John J. Ritsko,Russell J. Serino,D. Y. Shih,Janusz S. Wilczynski +12 more
TL;DR: The paper addresses the problems found on lossy lines, such as reflections, rise-time slowdown, increased delay, attenuation, and crosstalk, and suggests methods for controlling these effects in order to maintain distortion-free propagation of high-speed signals.
Journal ArticleDOI
Modeling and characterization of long on-chip interconnections for high-performance microprocessors
Alina Deutsch,G.V. Kopcsay,Barry J. Rubin,C.W. Surovic,L.M. Terman,R.P. Dunne,T. Gallo,R.H. Dennard +7 more
Proceedings ArticleDOI
Calculation of multi-port parameters of electronic packages using a general purpose electromagnetics code
Barry J. Rubin,S. Daijavad +1 more
TL;DR: In this article, a powerful code developed by the authors to solve radiation and scattering problems from arbitrary 3D dielectric-conductor structures is modified to provide the terminal characteristics of arbitrary package structures.
Proceedings ArticleDOI
A model and algorithm for interconnecting two WANs
S.-C. Liang,J.R. Yee +1 more
TL;DR: An algorithm to solve the problem of determining which gateways to use to interconnect existing wide area networks to minimize a linear combination of the average internet and intranet packet delays subject to a cost constraint on the amount to be spent to establish the gateways is developed.