Showing papers on "Adder published in 2013"

Low-Power Digital Signal Processing Using Approximate Adders

Abstract: Low power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. In most multimedia applications, human beings can gather useful information from slightly erroneous outputs. Therefore, we do not need to produce exactly correct numerical outputs. Previous research in this context exploits error resiliency primarily through voltage overscaling, utilizing algorithmic and architectural techniques to mitigate the resulting errors. In this paper, we propose logic complexity reduction at the transistor level as an alternative approach to take advantage of the relaxation of numerical accuracy. We demonstrate this concept by proposing various imprecise or approximate full adder cells with reduced complexity at the transistor level, and utilize them to design approximate multi-bit adders. In addition to the inherent reduction in switched capacitance, our techniques result in significantly shorter critical paths, enabling voltage scaling. We design architectures for video and image compression algorithms using the proposed approximate arithmetic units and evaluate them to demonstrate the efficacy of our approach. We also derive simple mathematical models for error and power consumption of these approximate adders. Furthermore, we demonstrate the utility of these approximate adders in two digital signal processing architectures (discrete cosine transform and finite impulse response filter) with specific quality constraints. Simulation results indicate up to 69% power savings using the proposed approximate adders, when compared to existing implementations using accurate adders.

New Metrics for the Reliability of Approximate and Probabilistic Adders

Abstract: Addition is a fundamental function in arithmetic operation; several adder designs have been proposed for implementations in inexact computing. These adders show different operational profiles; some of them are approximate in nature while others rely on probabilistic features of nanoscale circuits. However, there has been a lack of appropriate metrics to evaluate the efficacy of various inexact designs. In this paper, new metrics are proposed for evaluating the reliability as well as the power efficiency of approximate and probabilistic adders. Reliability is analyzed using the so-called sequential probability transition matrices (SPTMs). Error distance (ED) is initially defined as the arithmetic distance between an erroneous output and the correct output for a given input. The mean error distance (MED) and normalized error distance (NED) are then proposed as unified figures that consider the averaging effect of multiple inputs and the normalization of multiple-bit adders. It is shown that the MED is an effective metric for measuring the implementation accuracy of a multiple-bit adder and that the NED is a nearly invariant metric independent of the size of an adder. The MED is, therefore, useful in assessing the effectiveness of an approximate or probabilistic adder implementation, while the NED is useful in characterizing the reliability of a specific design. Since inexact adders are often used for saving power, the product of power and NED is further utilized for evaluating the tradeoffs between power consumption and precision. Although illustrated using adders, the proposed metrics are potentially useful in assessing other arithmetic circuit designs for applications of inexact computing.

Approximate XOR/XNOR-based adders for inexact computing

Abstract: Power dissipation has become a significant issue for integrated circuit design in nanometric CMOS technology To reduce power consumption, approximate implementations of a circuit have been considered as a potential solution for applications in which strict exactness is not required In inexact computing, power reduction is achieved through the relaxation of the often demanding requirement of accuracy In this paper, new approximate adders are proposed for low-power imprecise applications These adders are based on XOR/XNOR gates with multiplexers implemented by pass transistors The proposed approximate XOR/XNOR-based adders (AXAs) are evaluated and compared with respect to energy consumption, delay, area and power delay product (PDP) with an accurate full adder The metric of error distance is used to evaluate the reliability of the approximate designs Simulation by Cadence's Spectre in TSMC 65nm process has shown that the proposed designs consume less power and have better performance (such as a lower propagation delay) compared to the accurate XOR/XNOR-based adder, while the error distance remains similar or better than other approximate adder designs

On reconfiguration-oriented approximate adder design and its application

Abstract: Approximate circuit designs allow us to tradeoff computation quality (e.g., accuracy) and computational effort (e.g., energy), by exploiting the inherent error-resilience of many applications. As the computation quality requirement of an application generally varies at runtime, it is preferable to be able to reconfigure approximate circuits to satisfy such needs and save unnecessary computational effort. In this paper, we present a reconfiguration-oriented design methodology for approximate circuits, and propose a reconfigurable approximate adder design that degrades computation quality gracefully. The proposed design methodology enables us to achieve better quality-effort tradeoff when compared to existing techniques, as demonstrated in the application of DCT computing.

Low Power Magnetic Full-Adder Based on Spin Transfer Torque MRAM

Abstract: Power issues have become a major problem of CMOS logic circuits as technology node shrinks below 90 nm. In order to overcome this limitation, emerging logic-in-memory architecture based on nonvolatile memories (NVMs) are being investigated. Spin transfer torque (STT) magnetic random access memory (MRAM) is considered one of the most promising NVMs thanks to its high speed, low power, good endurance, and 3-D back-end integration. This paper presents a novel magnetic full-adder (MFA) design based on perpendicular magnetic anisotropy (PMA) STT-MRAM. It provides advantageous power efficiency and die area compared with conventional CMOS-only full adder (FA). Transient simulations have been performed to validate this design by using an industrial CMOS 40 nm design kit and an accurate STT-MRAM compact model including physical models and experimental measurements.

Concurrent implementation of all-optical half-adder and AND & XOR logic gates based on nonlinear photonic crystal

Abstract: A new design for concurrent implementation of all-optical half-adder and AND & XOR logic gates based on nonlinear photonic crystal ring resonator has been proposed. The finite different time domain and plane wave expansion methods are used to analyze the behavior of the structure. The ring resonator has a low switching time of about 0.85 ps and low switching power equal to $$277\,\text{ mW}/\upmu \text{m}^{2}$$ . The simulation results show that the contrast ratio is 12.78 dB for AND gate and 5.67 dB for XOR gate. Moreover, the operational wavelength of the input ports is $$1.55\,\upmu \text{m}$$ . Since the structure has a simple geometric shape with clear operating principle, it is potentially applicable for photonic integrated circuits.

An energy efficient approximate adder with carry skip for error resilient neuromorphic VLSI systems

Abstract: We propose a novel approximate adder design to significantly reduce energy consumption with a very moderate error rate. The significantly improved error rate and critical path delay stem from the employed carry prediction technique that leverages the information from less significant input bits in a parallel manner. An error magnitude reduction scheme is proposed to further reduce amount of error once detected with low cost. Implemented in a commercial 90 nm CMOS process, it is shown that the proposed adder is up to 2.4× faster and 43% more energy efficient over traditional adders while having an error rate of only 0.18%. The proposed adder has been adopted in a VLSI-based neuromorphic character recognition chip using unsupervised learning. The approximation errors of the proposed adder have been shown to have negligible impact on the training process. Moreover, the energy savings of up to 48.5% over traditional adders is achieved for the neuromorphic circuit with scaled supply level. Finally, we achieve error-free operations by including a low-overhead error correction logic.

Low Power and Area-Efficient Carry Select Adder

Abstract: Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA This work uses a simple and efficient gat e-level modification to significantly reduce the area and p ower of the CSLA Based on this modification 8-, 16-, 32-, and 64- b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 018-m CMOS process technology The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA Keywords—Application-specific integrated circuit (ASIC), area

Design of high speed hybrid carry select adder

Abstract: The paper describes the power and area efficient carry select adder (CSA). Firstly, CSA is one of the fastest adders used in many data-processing systems to perform fast arithmetic operations. Secondly, CSA is intermediate between small areas but longer delay Ripple Carry Adder (RCA) and a larger area with shorter delay carry look-ahead adder. Third, there is still scope to reduce area in CSA by introduction of some add-one scheme. In Modified Carry Select Adder (MCSA) design, single RCA and BEC are used instead of dual RCAs to reduce area and power consumption with small speed penalty. The reason for area reduction is that, the number of logic gates used to design a BEC is less than the number of logic gates used for a RCA design. Thus, importance of BEC logic comes from the large silicon area reduction when designing MCSA for large number of bits. MCSA architectures are designed for 8-bit, 16-bit, 32-bit and 64-bit respectively. The design has been synthesized at 90nm process technology targeting using Xilinx Spartan-3 device. Comparison results of modified CSA with conventional CSA show better results and improvements.

Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic

Abstract: This brief presents a novel pipelined architecture for low-power, high-throughput, and low-area implementation of adaptive filter based on distributed arithmetic (DA). The throughput rate of the proposed design is significantly increased by parallel lookup table (LUT) update and concurrent implementation of filtering and weight-update operations. The conventional adder-based shift accumulation for DA-based inner-product computation is replaced by conditional signed carry-save accumulation in order to reduce the sampling period and area complexity. Reduction of power consumption is achieved in the proposed design by using a fast bit clock for carry-save accumulation but a much slower clock for all other operations. It involves the same number of multiplexors, smaller LUT, and nearly half the number of adders compared to the existing DA-based design. From synthesis results, it is found that the proposed design consumes 13% less power and 29% less area-delay product (ADP) over our previous DA-based adaptive filter in average for filter lengths N = 16 and 32. Compared to the best of other existing designs, our proposed architecture provides 9.5 times less power and 4.6 times less ADP.

Magnetic Adder Based on Racetrack Memory

Abstract: The miniaturization of integrated circuits based on complementary metal oxide semiconductor (CMOS) technology meets a significant slowdown in this decade due to several technological and scientific difficulties. Spintronic devices such as magnetic tunnel junction (MTJ) nanopillar become one of the most promising candidates for the next generation of memory and logic chips thanks to their non-volatility, infinite endurance, and high density. A magnetic processor based on spintronic devices is then expected to overcome the issue of increasing standby power due to leakage currents and high dynamic power dedicated to data moving. For the purpose of fabricating such a non-volatile magnetic processor, a new design of multi-bit magnetic adder (MA)-the basic element of arithmetic/logic unit for any processor-whose input and output data are stored in perpendicular magnetic anisotropy (PMA) domain wall (DW) racetrack memory (RM)-is presented in this paper. The proposed multi-bit MA circuit promises nearly zero standby power, instant ON/OFF capability, and smaller die area. By using an accurate racetrack memory spice model, we validated this design and simulated its performance such as speed, power and area, etc.

Steep switching tunnel FET: a promise to extend the energy efficient roadmap for post-CMOS digital and analog/RF applications

Abstract: Steep switching Tunnel FETs (TFET) can extend the supply voltage scaling with improved energy efficiency for both digital and analog/RF application. In this paper, recent approaches on III-V Tunnel FET device design, prototype device demonstration, modeling techniques and performance evaluations for digital and analog/RF application are discussed and compared to CMOS technology. The impact of steep switching, uni-directional conduction and negative differential resistance characteristics are explored from circuit design perspective. Circuit-level implementation such as III-V TFET based Adder and SRAM design shows significant improvement on energy efficiency and power reduction below 0.3V for digital application. The analog/RF metric evaluation is presented including gm/Ids metric, temperature sensitivity, parasitic impact and noise performance. TFETs exhibit promising performance for high frequency, high sensitivity and ultra-low power RF rectifier application.

Energy-Efficient High-Throughput Montgomery Modular Multipliers for RSA Cryptosystems

Abstract: Modular exponentiation in the Rivest, Shamir, and Adleman cryptosystem is usually achieved by repeated modular multiplications on large integers. To speed up the encryption/decryption process, many high-speed Montgomery modular multiplication algorithms and hardware architectures employ carry-save addition to avoid the carry propagation at each addition operation of the add-shift loop. In this paper, we propose an energy-efficient algorithm and its corresponding architecture to not only reduce the energy consumption but also further enhance the throughput of Montgomery modular multipliers. The proposed architecture is capable of bypassing the superfluous carry-save addition and register write operations, leading to less energy consumption and higher throughput. In addition, we also modify the barrel register full adder (BRFA) so that the gated clock design technique can be applied to significantly reduce the energy consumption of storage elements in BRFA. Experimental results show that the proposed approaches can achieve up to 60% energy saving and 24.6% throughput improvement for 1024-bit Montgomery multiplier.

Design of efficient reversible logic-based binary and BCD adder circuits

Abstract: Reversible logic is gaining significance in the context of emerging technologies such as quantum computing since reversible circuits do not lose information during computation and there is one-to-one mapping between the inputs and outputs. In this work, we present a class of new designs for reversible binary and BCD adder circuits. The proposed designs are primarily optimized for the number of ancilla inputs and the number of garbage outputs and are designed for possible best values for the quantum cost and delay. In reversible circuits, in addition to the primary inputs, some constant input bits are used to realize different logic functions which are referred to as ancilla inputs and are overheads that need to be reduced. Further, the garbage outputs which do not contribute to any useful computations but are needed to maintain reversibility are also overheads that need to be reduced in reversible designs. First, we propose two new designs for the reversible ripple carry adder: (i) one with no input carry c0 and no ancilla input bits, and (ii) one with input carry c0 and no ancilla input bits. The proposed reversible ripple carry adder designs with no ancilla input bits have less quantum cost and logic depth (delay) compared to their existing counterparts in the literature. In these designs, the quantum cost and delay are reduced by deriving designs based on the reversible Peres gate and the TR gate. Next, four new designs for the reversible BCD adder are presented based on the following two approaches: (i) the addition is performed in binary mode and correction is applied to convert to BCD when required through detection and correction, and (ii) the addition is performed in binary mode and the result is always converted using a binary to BCD converter. The proposed reversible binary and BCD adders can be applied in a wide variety of digital signal processing applications and constitute important design components of reversible computing.

An efficient SQRT architecture of Carry Select adder design by Common Boolean logic

Abstract: Carry Select adder (CSLA) is known to be the fastest adder among the Conventional adder structures. This work uses an efficient Carry select adder by sharing the Common Boolean logic (CLB) term. After a logic simplification, we only need one OR gate and one inverter gate for carry and summation operation. Through the multiplexer, we can select the correct output according to the logic states of the carry in signal. Based on this modification Square root CSLA (SQRT CSLA) architecture have been developed and compared with the regular and Modified SQRT CSLA architecture. The Modified CSLA architecture has been developed using Binary to Excess -1 converter (BEC). This paper proposes an efficient method which replaces a BEC using common Boolean logic. The result analysis shows that the proposed architecture achieves the three folded advantages in terms of area, delay and power.

Experimental Demonstration of a 1-Bit Full Adder in Perpendicular Nanomagnetic Logic

Abstract: In this paper a 1-bit full adder realized in perpendicular nanomagnetic logic (pNML) is presented for the first time. The theory of NML with perpendicular magnetic anisotropy is introduced illustrating the great benefit of the universal majority decision. The working principle of complex logic circuits is experimentally demonstrated utilizing the presented full adder. Partial focused ion beam irradiation is used to control the anisotropy locally and tailor the magnetic behavior of the nanomagnets. A full adder structure consisting of 3 majority gates and 4 inverters is realized on an area of 17 um . Global, alternating field pulses with constant amplitude are used as power clock. MFM measurements demonstrate the functionality of the structure and the validity of the introduced theory. The presented work proves the working principle of non-volatile, field-coupled logic and demonstrates the feasibility of complex logic circuits in perpendicular nanomagnetic logic.

Design of efficient full adder in quantum-dot cellular automata.

Abstract: Further downscaling of CMOS technology becomes challenging as it faces limitation of feature size reduction. Quantum-dot cellular automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. Investigations on the reduction of QCA primitives (majority gates and inverters) for various adders are limited, and very few designs exist for reference. As a result, design of adders under QCA framework is gaining its importance in recent research. This work targets developing multi-layered full adder architecture in QCA framework based on five-input majority gate proposed here. A minimum clock zone (2 clock) with high compaction (0.01 μm2) for a full adder around QCA is achieved. Further, the usefulness of such design is established with the synthesis of high-level logic. Experimental results illustrate the significant improvements in design level in terms of circuit area, cell count, and clock compared to that of conventional design approaches.

Architectural enhancements in Stratix V

Abstract: This paper describes architectural enhancements in the Altera Stratix-V" FPGA architecture, built on a 28nm TSMC process, together with the data supporting those choices. Among the key features are time borrowing flip-flops, a doubling of the number of flip-flops per LUT compared to previous Stratix architectures, a simplified embedded 20kb dual-port RAM block, and error correction that can correct up to 8 adjacent errors. Arithmetic performance is significantly improved using a fast adder with two levels of multi-bit skip. We also describe how the routing architecture and layout is optimized for the 28nm process to take advantage of a wider range of wire thicknesses offered on the different layers, and improvements in performance and routability are obtained without dramatic changes to the repeated floorplan of the logic plus routing fabric.

Circuit-Level Timing Error Tolerance for Low-Power DSP Filters and Transforms

Abstract: In this paper, we present a novel circuit-level timing error mitigation technique, which aims to increase energy-efficiency of digital signal processing datapaths without loss of robustness. Timing errors are detected using razor flip-flops on critical-paths, and the error-rate feedback is used to control a dynamic voltage scaling control loop. In place of conventional razor error correction by replay, we propose a new approach to bound the magnitude of intermittent timing errors at the circuit level. A timing guard-band is created by shaping the path delay distribution such that the critical paths correspond to a group of least-significant bit registers. These end-points are ensured to be critical by modifying the topology of the final stage carry-merge adder, and by using tool-based device sizing. Hence, timing violations lead to weakly correlated logical errors of small magnitude in a mean-squared-error sense. We examine this approach in an finite-impulse response (FIR) filter and a 2-D discrete cosine transform implementation, in 32-nm CMOS. Power saving compared to a conventional design at iso-frequency is 21%-23% at the typical corner, while retaining a voltage guard-band to protect against fast transient changes in switching activity and supply noise. The impact on minimum clock period is small (16%-20%), as it does not necessitate the use of ripple-carry adders and also requires only a bare minimum of additional design effort.

An 8-bit carry look-ahead adder with 150 ps latency and sub-microwatt power dissipation at 10 GHz

Abstract: Reciprocal quantum logic combines the speed and power-efficiency of single-flux quantum superconductor devices with design features that are similar to CMOS. We have demonstrated an 8-bit carry look-ahead adder in the technology using combinational gates with fanout of four and non-local interconnect. Measured power dissipation of the fully active circuit is only 510 nW at 6.2 GHz. Latency is only 150 ps at a clock rate of 10 GHz.

Implementation of half adder and half subtractor with a simple and universal DNA-based platform

Abstract: As a powerful material, DNA presents great advantages in the fabrication of molecular devices and higher-order logic circuits. Herein, by making use of the hybridization and displacement of DNA strands, as well as the formation and dissociation of a G-quadruplex, a simple and universal DNA-based platform is developed to implement half-adder and half-subtractor arithmetic processes. The novel feature of the designed system is that the two required logic gates for the half adder (an AND and an XOR logic gate integrated in parallel) or the half subtractor (an XOR and an INHIBIT logic gate integrated in parallel) are achieved simultaneously with the same platform and are triggered by the same set of inputs. Another novel feature is that the developed half adder and half subtractor are operated by the same DNA platform in an enzyme-free system and share a constant threshold setpoint. These investigations provide a new route towards prototypical DNA-based arithmetic operations and promote the development of advanced logic circuits.

Analysis and Comparison: Full Adder Block in Submicron Technology

Abstract: The reduction in the operating voltage play a majorrole in improving the performance of the integratedcircuits.Apart from that lesser power consumption, reducedarea and smaller size of transistors are also the vital factors inthe design criteria and fabrication of the systems. This articleapproaches towards the increasing performance of the systemsby comparing different types of adder circuits. In this article, anew circuit has been designed using the TG technology. Basedon different parameters like average power consumption anddelay, it has been observed that the Carry look-ahead adderand Carry bypass adder consumes more power. TheComparative analysis of TG based 8-bit different AdderDesigns using 180nm technology using TANNER tool has beenconsidered.

A Scalable Signal Distribution Network for Quantum-Dot Cellular Automata

Abstract: The authors describe a signal distribution network (SDN) for quantum-dot cellular automata (QCA) devices. This network allows the distribution of a set of inputs to an arbitrary number of combinational functions, overcoming the challenges associated with wire crossings that have faced QCA systems for many years. As an additional benefit, the proposed SDN requires only four distinct clock signals, regardless of the number of inputs or outputs, and those clock signals each repeat a very simple pattern. Furthermore, this network is highly scalable, completing the distribution of inputs to an arbitrary number of distributed signals and an arbitrary number of outputs in 4 - 2 clock cycles. To illustrate its operation, the authors apply the SDN to a two-input/one-output exclusive OR operation, a three-input/two-output full adder, and a four-input/four-output multiplier.

A New RNS based DA Approach for Inner Product Computation

Abstract: This paper presents a novel method to perform inner product computation based on the distributed arithmetic principles. The input data are represented in the residue domain and are encoded using the thermometer code format while the output data are encoded in the one-hot code format. Compared to the conventional distributed arithmetic based system using binary coded format to represent the residues, the proposed system using the thermometer code encoded residues provides a simple means to perform the modular inner products computation due to the absence of the 2 modulo operation encountered in conventional binary code encoded system. In addition, the modulo adder used in the proposed system can be implemented using simple shifter based circuit utilizing one-hot code format. As there is no carry propagation involved in the addition using one-hot code, while the modulo operation can be performed automatically during the addition process, the operating speed of the one-hot code based modulo adder is much superior compared to the conventional binary code based modulo adder. As inner product is used extensively in FIR filter design, SPICE simulation results for an FIR filter implemented using the proposed system is also presented to demonstrate the validity of the proposed scheme.

Efficient Multiternary Digit Adder Design in CNTFET Technology

Abstract: This letter presents an efficient multiternary digit (trit) adder design in carbon nanotube field effect transistor technology. The adder is based on an efficient single-trit full-adder design with low-complexity encoder and reduced complexity carry-generation unit. Further, we optimize the number of encoder and decoder blocks required while putting together several single-trit full-adder units to realize a multitrit adder. Extensive HSPICE simulation results show roughly 79% reduction in power-delay product for three-trit adders and 88 $\hbox{\%}$ reduction in power-delay product for nine-trit adders in comparison to a direct realization.

Digital logic with molecular reactions

Abstract: This paper presents a methodology for implementing digital logic with molecular reactions based on a bistable mechanism for representing bits. The value of a bit is not determined by the concentration of a single molecular type; rather, it is the comparison of the concentrations of two complementary types that determines if the bit is "0" or "1". This mechanism is robust: any small perturbation or leakage in the concentrations quickly gets cleared out and the signal value is not affected. Based on this representation for bits, a constituent set of logical components are implemented. These include combinational components -- AND, OR, NOR, and XOR -- as well as sequential components -- D latches and D flip-flops. Using these components, three full-fledged design examples are given: a square-root unit, a binary adder and a linear feedback shift register. DNA-based computation via strand displacement is the target experimental chassis. The designs are validated through simulations of the chemical kinetics. The simulations show that the molecular systems compute digital functions accurately and robustly.

Experimental Realization of a Nanomagnet Full Adder Using Slanted-Edge Magnets

Abstract: We present the experimental realization of a full adder circuit using Nanomagnet Logic (NML). The circuit relies heavily on the properties of asymmetric slant magnets that allow robust operation and reduced footprint. We demonstrate stand-alone NML majority gates and wires, and interconnect these components into an NML full adder that functions properly for all 8 input combinations. To our knowledge, this is the first working implementation of an NML full adder from in-plane magnetized nanomagnets, and one of the very few existing non-electrical, room temperature nanoscale computing units.

A novel high-performance CMOS 1 bit full-adder cell

Abstract: In this paper we propose a low complexity full adder design featuring higher computing speed, lower operating voltage, and lower energy consumption. it uses the low power designs of the XOR and AND gates pass transistors and transmission gates, simulation results comparing the conventional cell to the standard implementation show its superiority different circuit structures and input patterns are used for simulation. Energy saving up to 40% is achieved in addition. The performance is edge of the proposed. Design in both speed and energy consumption becomes even more significant as the world length of the adder increases. we explain how exclusive (XOR/AND) are used to realize a general full adder circuit based on pass transistor, the performance of the proposed full adder is evaluated by the comparison of the simulation result obtained from cadence. There is a higher cost in terms of the design effort for the proposed adder.

Progress in Reversible Processor Design: A Novel Methodology for Reversible Carry Look-Ahead Adder

Abstract: Reversible logic is playing a significant role in quantum computing as quantum operations are unitary in nature. Quantum computer performs computation at an atomic level; thereby doing high performance computations beyond the limits of the conventional computing systems. Reversible arithmetic units such as adders, subtractors, multipliers form the essential component of a quantum computing system. Among the adder designs, carry look-ahead is widely used in high performance computing due to its O (log n) depth. In this work, we present improved designs of both in-place and out-of-place reversible carry look-ahead adder proposed in [1]. The proposed designs utilize the properties of the reversible Peres gate and the TR gate to optimize the logic depth, quantum cost and gate count compared to the existing designs proposed in [1]. Both the improved designs assume no input carry (C0=0). While the first approach makes use of ancilla bits to store the sum outputs, the second approach stores the sum outputs in one of the input locations.