Showing papers on "BCH code published in 2010"

Polar Codes: Characterization of Exponent, Bounds, and Constructions

Abstract: Polar codes were recently introduced by Arikan. They achieve the symmetric capacity of arbitrary binary-input discrete memoryless channels under a low complexity successive cancellation decoding scheme. The original polar code construction is closely related to the recursive construction of Reed-Muller codes and is based on the 2 × 2 matrix [1 0 : 1 1]. It was shown by Arikan Telatar that this construction achieves an error exponent of 1/2, i.e., that for sufficiently large blocklengths the error probability decays exponentially in the square root of the blocklength. It was already mentioned by Arikan that in principle larger matrices can be used to construct polar codes. In this paper, it is first shown that any l × l matrix none of whose column permutations is upper triangular polarizes binary-input memoryless channels. The exponent of a given square matrix is characterized, upper and lower bounds on achievable exponents are given. Using these bounds it is shown that there are no matrices of size smaller than 15×15 with exponents exceeding 1/2. Further, a general construction based on BCH codes which for large I achieves exponents arbitrarily close to 1 is given. At size 16 × 16, this construction yields an exponent greater than 1/2.

Error characterization and coding schemes for flash memories

Abstract: In this work, we use an extensive empirical database of errors induced by write, read, and erase operations to develop a comprehensive understanding of the error behavior of flash memories. Error characterization of MLC and SLC flash is given on the block, page, and bit level. Based on our error characterization in MLC flash, we propose an error-correcting scheme which outperforms the conventional BCH code. We compare several schemes which use an MLC block as an SLC block. Finally, an implementation of two-write WOM-codes in SLC flash is given as well as the BER for the first and second write.

Multibit Error-Correction Methods for Latency-Constrained Flash Memory Systems

Abstract: This paper presents multibit error-correction schemes for nor Flash used specifically for execute-in-place applications. As architectures advance to accommodate more bits/cell and geometries decrease to structures that are smaller than 32 nm, single-bit error-correction codes (ECCs) are unable to compensate for the increasing array bit error rates, making it imperative to use 2-b ECC. However, 2-b ECC algorithms are complex and add a timing overhead on the memory read access time. This paper proposes low-latency multibit ECC schemes. Starting with the binary Bose-Chaudhuri-Hocquenghem (BCH) codes, an optimized scheme is introduced which combines a multibit error-correcting BCH code with Hamming codes in a hierarchical manner to give an average latency as low as that of the single-bit correcting Hamming decoder. A Hamming algorithm with 2-b error-correcting capacity for very small block sizes (< 1 B) is another low-latency multibit ECC algorithm that is discussed. The viability of these methods and algorithms with respect to latency and die area is proved vis-a?-vis software and hardware implementations.

VLSI Implementation of BCH Error Correction for Multilevel Cell NAND Flash Memory

Abstract: Bit-error correction is crucial for realizing cost-effective and reliable NAND Flash-memory-based storage systems. In this paper, low-power and high-throughput error-correction circuits have been developed for multilevel cell (MLC) nand Flash memories. The developed circuits employ the Bose-Chaudhuri-Hocquenghem code to correct multiple random bit errors. The error-correcting codes for them are designed based on the bit-error characteristics of MLC NAND Flash memories for solid-state drives. To trade the code rate, circuit complexity, and power consumption, three error-correcting architectures, named as whole-page, sector-pipelined, and multistrip ones, are proposed. The VLSI design applies both algorithmic and architectural-level optimizations that include parallel algorithm transformation, resource sharing, and time multiplexing. The chip area, power consumption, and throughput results for these three architectures are presented.

Self-Adaptive System for Addressing Permanent Errors in On-Chip Interconnects

Abstract: We present a self-contained adaptive system for detecting and bypassing permanent errors in on-chip interconnects. The proposed system reroutes data on erroneous links to a set of spare wires without interrupting the data flow. To detect permanent errors at runtime, a novel in-line test (ILT) method using spare wires and a test pattern generator is proposed. In addition, an improved syndrome storing-based detection (SSD) method is presented and compared to the ILT method. Each detection method (ILT and SSD) is integrated individually into the noninterrupting adaptive system, and a case study is performed to compare them with Hamming and Bose-Chaudhuri-Hocquenghem (BCH) code implementations. In the presence of permanent errors, the probability of correct transmission in the proposed systems is improved by up to 140% over the standalone Hamming code. Furthermore, our methods achieve up to 38% area, 64% energy, and 61% latency improvements over the BCH implementation at comparable error performance.

Improving Multi-Level NAND Flash Memory Storage Reliability Using Concatenated BCH-TCM Coding

Abstract: By storing more than one bit in each memory cell, multi-level per cell (MLC) NAND flash memories are dominating global flash memory market due to their appealing storage density advantage. However, continuous technology scaling makes MLC NAND flash memories increasingly subject to worse raw storage reliability. This paper presents a memory fault tolerance design solution geared to MLC NAND flash memories. The basic idea is to concatenate trellis coded modulation (TCM) with an outer BCH code, which can greatly improve the error correction performance compared with the current design practice that uses BCH codes only. The key is that TCM can well leverage the multi-level storage characteristic to reduce the memory bit error rate and hence relieve the burden of outer BCH code, at no cost of extra redundant memory cells. The superior performance of such concatenated BCH-TCM coding systems for MLC NAND flash memories has been well demonstrated through computer simulations. A modified TCM demodulation approach is further proposed to improve the tolerance to static memory cell defects. We also address the associated practical implementation issues in case of using either single-page or multi-page programming strategy, and demonstrate the silicon implementation efficiency through application-specific integrated circuit design at 65 nm node.

Continuously-interleaved BCH (CI-BCH) FEC delivers best in class NECG for 40G and 100G metro applications

Abstract: We provide 40G OTU3 performance results for Continuously-Interleaved concatenated BCH (CI-BCH) FEC, demonstrating best-in-class performance for a 7% overhead hard-decision FEC and offers option to tradeoff coding gain for reduced FEC decode latency.

BCH coding and intelligent watermark embedding: Employing both frequency and strength selection

Abstract: This paper presents a novel approach of adaptive visual tuning of a watermark in Discrete Cosine Transform (DCT) domain. The proposed approach intelligently selects appropriate frequency bands as well as optimal strength of alteration. Genetic Programming (GP) is applied to structure the watermark by exploiting both the characteristics of human visual system and information pertaining to a cascade of conceivable attacks. The developed visual tuning expressions are dependent on frequency and luminance sensitivities, and contrast masking. To further enhance robustness, spread spectrum based watermarking and Bose-Chadhuri-Hocquenghem (BCH) coding is employed. The combination of spread spectrum sequence, BCH coding and GP based non-linear structuring makes it extremely difficult for an attacker to gain information about the secret knowledge of the watermarking system. Experimental results show the superiority of the proposed approach against the existing approaches. Especially, the margin of improvement in robustness will be of high importance in medical and context aware related applications of watermarking.

Memory system and control method for the same

Abstract: A memory system having a memory card configured to store frame data composed of a plurality of pieces of sector data and a host configured to send and receive the frame data to and from the memory card, the memory card includes: an ECC1 decoder configured to perform BCH decoding processing with a hard decision code on a sector data basis; an ECC2 decoder configured to perform LDPC decoding processing with an LDPC code on a frame data basis; a sector error flag section configured to store information about presence or absence of error data in the BCH decoding processing; and an ECC control section configured to perform, in the LDPC decoding processing, control of increasing a reliability of sector data containing no error data based on the information in the sector error flag section

Generalization of Steane's Enlargement Construction of Quantum Codes and Applications

Abstract: We generalize Steane's enlargement construction of binary quantum codes to q-ary quantum codes. We then apply this result to BCH codes and the study of asymptotic bounds, and obtain improvements to the quantum BCH codes constructed by Aly and Klappenecker and the quantum asymptotic bounds from algebraic geometry codes obtained by Feng, Ling, and Xing.

Error correcting coding for OTN

Abstract: Forward error correction codes for 100 Gb/s optical transmission are currently receiving much attention from transport network operators and technology providers. We discuss the performance of hard decision decoding using product type codes that cover a single OTN frame or a small number of such frames. In particular we argue that a three-error correcting BCH is the best choice for the component code in such systems.

A Separation Algorithm for Improved LP-Decoding of Linear Block Codes

Abstract: Maximum likelihood (ML) decoding is the optimal decoding algorithm for arbitrary linear block codes and can be written as an integer programming (IP) problem. Feldman relaxed this IP problem and presented linear programming (LP) based decoding. In this paper, we propose a new separation algorithm to improve the error-correcting performance of LP decoding for binary linear block codes. We use an IP formulation with indicator variables that help in detecting the violated parity checks. We derive Gomory cuts from the IP and use them in our separation algorithm. An efficient method of finding cuts induced by redundant parity checks (RPC) is also proposed. Under certain circumstances we can guarantee that these RPC cuts are valid and cut off the fractional optimal solutions of LP decoding. It is demonstrated on three LDPC codes and two BCH codes that our separation algorithm performs significantly better than LP decoding and belief propagation (BP) decoding.

Error Correction Codes in Wireless Sensor Network: An Energy Aware Approach

Abstract: Link reliability and transmitted power are two important design constraints in wireless network design. Error control coding (ECC) is a classic approach used to increase link reliability and to lower the required transmitted power. It provides coding gain, resulting in transmitter energy savings at the cost of added decoder power consumption. But the choice of ECC is very critical in the case of wireless sensor network (WSN). Since the WSNs are energy constraint in nature, both the BER and power consumption has to be taken into count. This paper develops a step by step approach in finding suitable error control codes for WSNs. Several simulations are taken considering different error control codes and the result shows that the RS(31,21) fits both in BER and power consumption criteria. Keywords—Error correcting code, RS, BCH, wireless sensor networks

Error-locality-aware linear coding to correct multi-bit upsets in SRAMs

Abstract: High-energy cosmic radiation is the major source of soft errors in SRAMs that can cause multi-bit upset around the location of the strike. In this paper, we generalize the coding problem for error detection and correction of both local (burst) and global (random) errors. We suggest using error-locality-aware codes for SRAM memories to correct single-bit or multi-bit upsets as well as physical defects. Solving the coding problem with a SAT-solver, we have found codes to correct double global or multiple (>=3) local errors for 8, 12, 16, and 24-bit memories. For 16-bit memories, we propose a code that corrects two global or four local errors. With the same cost, our proposed code provides extra reliability than double-error-correcting BCH code. For 12-bit memories, we suggest a code that corrects two global or five local errors and has the same cost as triple-error-correcting Golay code but provides better reliability against multi-bit upsets. For memories of other widths, using syndrome analysis, we demonstrate the possibility of designing codes to correct any arbitrary number of local and global errors.

Concatenated Coded Modulation for Optical Communications Systems

Abstract: The use of trellis-coded modulation (TCM) in combination with an outer block code is considered for next-generation 100-Gb/s optical transmission systems. Two block codes are employed as an outer code: a 16 times interleaved byte-oriented (255,239) Reed Solomon (RS) code and a code consisting of two interleaved extended three-error correcting Bose Chaudhuri Hocquenghem (BCH) (1020,988) codes. Simulations show that soft-decision decoding of a selected TCM inner code in combination with hard-decision decoding of the outer RS code achieves a net coding gain (NCG) of 8.42 dB at a bit-error rate of 10-13. When the concatenated code based on the two interleaved BCH codes is used as the outer code, the NCG is 9.7 dB. The impact of quantization on the performance of the concatenated TCM scheme with the two interleaved BCH outer codes is evaluated, and it is shown that 4-bit quantization is sufficient to approach the "infinite precision" performance to within 0.15 dB.

Communication device employing LDPC (Low Density Parity Check) coding with Reed-Solomon (RS) and/or binary product coding

Abstract: Communication device employing LDPC (Low Density Parity Check) coding with Reed-Solomon (RS) and/or binary product coding. An LDPC code is concatenated with a RS code or a binary product code (e.g., using row and column encoding of matrix formatted bits) thereby generating coded bits for use in generating a signal that is suitable to be launched into a communication channel. Various ECCs/FECs may be employed including a BCH (Bose and Ray-Chaudhuri, and Hocquenghem) code, a Reed-Solomon (RS) code, an LDPC (Low Density Parity Check) code, etc. and various implementations of cyclic redundancy check (CRC) may accompany the product coding and/or additional ECC/FEC employed. The redundancy of such coded signals as generated using the principles herein are in the range of approximately 20% thereby providing a significant amount of redundancy and a high coding gain. Soft decision decoding may be performed on such coded signal generated herein.

Algorithms for memories with stuck cells

Abstract: We present a class of algorithms for encoding data in memories with stuck cells. These algorithms rely on earlier code constructions termed cyclic Partitioned Linear Block Codes. For the corresponding q-ary BCH-like codes for u stucks in a codeword of length n, our encoding algorithm has complexity O((u log q n)2) F q operations, which we will show compares favorably to a generic approach based on Gaussian elimination. The computational complexity improvements are realized by taking advantage of the algebraic structure of cyclic codes for stucks. The algorithms are also applicable to cyclic codes for both stucks and errors.

Soft Information Relaying for Distributed Turbo Product Codes (SIR-DTPC)

Abstract: In this letter, we propose a distributed turbo product code (DTPC) with soft information relaying over cooperative network using block extended Bose Chaudhuri Hochquenghem (EBCH) codes as component codes. The source broadcasts extended EBCH coded frames to the destination and to a preassigned relay. After soft-decoding, the received sequences and obtaining the log-likelihood ratio (LLR) values, the relay constructs a product code by arranging the decoded bit sequences in rows and re-encoding them along the columns using a novel soft block encoding technique to obtain soft parity bits with different reliabilities that can be used as soft incremental redundancy (IR) that is forwarded to the destination. We compared the simulation results in additive white Gaussian noise (AWGN) channel with our previous work for decode-and-forward (DF) DTPC and with noncooperative case. The proposed system shows better bit error rate (BER) performance and less sensitivity to the relay's position.

Reliable MLC NAND flash memories based on nonlinear t-error-correcting codes

Abstract: Multi-level cell (MLC) NAND flash memories are very popular storage media because of their power efficiency and big storage density. This paper proposes to use nonlinear t-error-correcting codes to replace linear BCH codes for error detection and correction in MLC NAND flash memories. Compared to linear BCH codes with the same bit-error correcting capability t, the proposed codes have less errors miscorrected by all codewords and nearly no undetectable errors. For example, the proposed (8281, 8201, 11) 5-error-correcting code has no errors of multiplicity six miscorrected by all codewords while the widely used (8262, 8192, 11) linear shortened BCH code has 11 over 6 × A 11 errors in this class, where A 11 ≈ 1014 is the number of codewords of Hamming weight eleven in the shortened BCH code. Moreover, in spite of the fact that the Hamming distance of the proposed code is 2t+1, it can also correct some errors of multiplicity t+1 and t+2 requiring no extra hardware overhead and latency penalty. In this paper, the constructions and the error correction algorithm for the nonlinear t-error-correcting codes are presented. The architecture of the encoder and the decoder for the codes are shown. The error correcting capabilities, the hardware overhead, the latency and the power consumption for the encoder and the decoder will be analyzed and compared to that of the linear BCH codes to demonstrate the advantages of the proposed codes for error detection and correction in MLC NAND flash memories.

Reliability model for extending cluster lifetime using Backup Cluster Heads in cluster-based Wireless Sensor Networks

Abstract: In cluster-based two-tier Wireless Sensor Networks (WSNs), the cluster-head nodes (CHs) gather data from sensors and then transmit to the base station. When these cluster head nodes start to die, the coverage of the respective clusters is lost and it leaves the region unmonitored. Even if the CHs are rotated and reassigned after some time, until the next rotation that cluster in question will be out of cluster head, causing a loss of information and loss of coverage. To select a Backup Cluster Head (BCH) is suggested for those CHs which are close to deplete their energy [1]. When the CH dies, BCH takes over the responsibility and continues to work as a new cluster head. In this paper we present an analytical model of cluster reliability in cluster-based WSN using BCH, based on Markov chain model. We use non-homogeneous Markov process, along with Forward Chapman-Kolmogorov equations to illustrate the cluster monitoring period in a finite three state space model. We test the accuracy of the model by applying the probabilities of failure of CH and BCH nodes, for a fixed number of sensor nodes in a cluster. The results show that the presented model is able to match the behaviour of the cluster state transition accurately and validates the simulation results and analysis published in [1].

Improved Coding-Theoretic and Subspace-Based Decoding Algorithms for a Wider Class of DCT and DST Codes

Abstract: The decoding of a class of discrete cosine transform (DCT) and discrete sine transform (DST) codes that are maximum distance separable codes (MDS) is considered in this paper. These class of codes are considered for error correction over real fields. All the existing algebraic decoding algorithms are capable of decoding only a subclass of these codes [which can be characterized into the Bose-Chaudhuri-Hocquenghem (BCH) form], and fails to decode the remaining even though they are MDS. In this paper, we propose a new generic algorithm along the lines of coding theoretic and subspace methods to decode the entire class of MDS DCT and DST codes. The proposed subspace approaches are similar to popular ESPRIT and MUSIC algorithms. The proposed algorithms also perform significantly better than the existing algorithms on the BCH-like subclass. A perturbation analysis is also presented to study the effect of various parameters on the error localization due to the quantization noise. Simulation results are presented to demonstrate the capability of proposed algorithms to decode the entire class and to perform significantly better on the BCH-like subclass than the existing algorithm under the influence of quantization noise.

Improving Burst Error Tolerance of LDPC-Centric Coding Systems in Read Channel

Abstract: We report on the use of low-density parity check (LDPC)-centric error correction coding (ECC) for magnetic recording read channel in the presence of significant burst errors. Since an LDPC code by itself is severely vulnerable to burst errors due to its soft-decision probability-based decoding, we focus on LDPC-centric concatenated coding in which LDPC code is used as inner code. To improve the burst error tolerance, we propose a hybrid LDPC-centric concatenated coding strategy in which one inner LDPC codeword is replaced by another codeword with much stronger burst error correction capability. This special inner codeword reveals the burst error location information, which can be leveraged by the inner LDPC code decoding to largely improve the overall robustness to burst errors. Using a hybrid BCH-LDPC/RS concatenated coding system as a test vehicle, we demonstrate a significant performance advantage over its RS-only and LDPC-only counterparts in the presence of three different types of burst errors.

DNA sequences generated by BCH codes over GF(4)

Abstract: The question raised by researchers in the field of mathematical biology regarding the existence of error-correcting codes in the structure of the DNA sequences is answered positively It is shown, for the first time, that DNA sequences such as proteins, targeting sequences and internal sequences are identified as codewords of BCH codes over Galois fields

Nonbinary Quantum Cyclic and Subsystem Codes Over Asymmetrically-decohered Quantum Channels

Abstract: Quantum computers theoretically are able to solve certain problems more quickly than any deterministic or probabilistic computers. A quantum computer exploits the rules of quantum mechanics to speed up computations. However, one has to mitigate the resulting noise and decoherence effects to avoid computational errors in order to successfully build quantum computers. In this paper, we construct asymmetric quantum codes to protect quantum information over asymmetric quantum channels, $\Pr Z \geq \Pr X$. Two generic methods are presented to derive asymmetric quantum cyclic codes using the generator polynomials and defining sets of classical cyclic codes. Consequently, the methods allow us to construct several families of quantum BCH, RS, and RM codes over asymmetric quantum channels. Finally, the methods are used to construct families of asymmetric subsystem codes.

Distributed Turbo Product Codes over Multiple Relays

Abstract: In this paper, we propose a Distributed Turbo Product Code (DTPC) over cooperative network using block Bose Chaudhuri Hochquenghem (BCH) codes as component codes. The source broadcasts extended BCH coded frames to the destination and nearby relays. After decoding the received sequences, each relay constructs a product code by arranging the corrected bit sequences in rows and re-encoding them vertically using BCH as component codes to obtain an Incremental Redundancy (IR) for source's data. To obtain independent vertical parities from each relay in the same code space, different circular interleavers are proposed to interleave BCH rows before reencoding vertically. A modified turbo product decoder to cope with Multiple Vertical Parities (MVP) is used at the destination to iteratively decode the systematic data from the source and the vertical parities generated by the relays. Simulation results in Additive White Gaussian Noise (AWGN) channel using network scenarios show 0.3-0.5dB gain improvement in Bit Error Rate (BER) performance over the non-cooperative Turbo Product Codes (TPC).

Error correction mechanisms for flash memories

Abstract: Methods and apparatuses for Bose-Chaudhuri-Hocquenghem (BCH) decoding utilizing Berlekamp-Massey Algorithm (BMA) and Chien Search. The BMA may utilize one or more of a scalable semi-parallel shared multiplier array, a conditional q-ary inversionless BMA and/or a conditional binary Inversionless BMA. The Chien Search may be accomplished utilizing a non-rectangular multiplier array.

A high-performance concatenated BCH code and its hardware architecture for 100 Gb/s long-haul optical communications

Abstract: This paper presents a six-iteration concatenated Bose-Chaudhuri-Hocquenghem (BCH) code and its high-speed two-parallel decoder architecture for 100 Gb/s optical communications. The proposed architecture features a very high data processing rate as well as excellent error correction capability. The proposed six-iteration concatenated BCH code structure with a block interleaving methods allows the decoder to achieve 9.19 dB net coding gain performance at 10−15 decoder output bit error rate to compensate for serious transmission quality degradation. Also, the proposed high-speed concatenated BCH decoder architecture was implemented to support 100 Gb/s data processing rate. Thus, it has potential applications in next generation forward error correction schemes for 100 Gb/s long-haul optical communications.

Encoding method and device thereof and decoding method and device thereof

Abstract: The invention provides a forward error correction encoding method, comprising the following steps: encoding the data stream according to the Reed-Solomon (RS) rules; interweaving the data stream afterbeing encoded by RS to serve as the input data stream of the BCH encoding; and encoding the data stream after being interwoven according to the BCH rules Accordingly, the invention also provides a forward error correction encoding device which is characterized by comprising an RS encoding module, an interweaving module and a BCH encoding module Accordingly, the invention also provides a forwarderror correction decoding method, comprising the following steps: decoding the data stream according to the BCH rules; de-interweaving the data stream after being decoded by the BCH rules to serve asthe input data stream of the RS decoding; and decoding the data stream after being de-interwoven according to the RS rules The invention provides a forward error correction device which is characterized by comprising a BCH decoding module, a de-interweaving module and an RS decoding module The method and device above realize the forward error correction with higher gain

Method, device, and digital circuity for providing a closed-form solution to a scaled error locator polynomial used in bch decoding

Abstract: A method of determining positions of one or more error bits is disclosed. The method includes receiving a BCH codeword at input circuitry of a decoder device, establishing a threshold number of correctable bits, and determining from the received BCH codeword and a root of an encoder polynomial, a value of each of one or more syndromes. The number of the one or more syndromes is twice a maximum number of correctable bits in the received BCH codeword. When the maximum number of correctable bits in the received BCH codeword is less than the threshold number of correctable bits, the value of each coefficient in a scaled error locator polynomial is determined by performing a non-iterative, closed-form solution on the scaled error locator polynomial. The scaled error locator polynomial is an original error locator polynomial scaled by a constant scale factor. The constant scale factor is determined according to the value of each of the one or more syndromes. Having determined the value of each coefficient in the scaled error locator polynomial, one or more roots of the scaled error locator polynomial are obtained. Each of the one or more roots indicates a position of an error bit. A BCH decoder device that can implement the method and a digital circuit that preserves operations implementing the method are also disclosed.