Showing papers on "Clock generator published in 2020"

Rail-to-Rail Timing Signals Generation Using InGaZnO TFTs For Flexible X-Ray Detector

Abstract: This paper reports on-chip rail-to-rail timing signals generation thin-film circuits for the first time. These circuits, based on a-IGZO thin-film transistors (TFTs) with a simple staggered bottom gate structure, allow row and column selection of a sensor matrix embedded in a flexible radiation sensing system. They include on-chip clock generator (ring oscillator), column selector (shift register) and row-selector (a frequency divider and a shift register). They are realised with rail-to-rail logic gates with level-shifting ability that can perform inversion and NAND logic operations. These logic gates are capable of providing full output swing between supply rails, V DD and V SS , by introducing a single additional switch for each input in bootstrapping logic gates. These circuits were characterised under normal ambient atmosphere and show an improved performance compared to the conventional logic gates with diode connected load and pseudo CMOS counterparts. By using these high-performance logic gates, a complete rail-to-rail frequency divider is presented from measurements using D-Flip Flop. In order to realize a complete compact system, an on-chip ring oscillator (output clock frequency around 1 kHz) and a shift register are also presented from simulations, where these circuits show a power consumption of 1.5 mW and 0.82 mW at a supply voltage of 8 V, respectively. While the circuit concepts described here were designed for an X-ray sensing system, they can be readily expanded to other domains where flexible on-chip timing signal generation is required, such as, smart packaging, biomedical wearable devices and RFIDs.

SSTRNG: self starved feedback SRAM based true random number generator using quantum cellular automata

Abstract: The information are need to modulate using irreproducible and unpredictable digital bit stream to get a secure digital communication systems. Hence, True random number generator (TRNG) is a significant aspirant in digital circuit to yield unpredictable digital bit stream. In this assignment self starved feedback SRAM based TRNG is proposed in quantum cellular automata (QCA) technology. Moreover, QCA technology is adopted to design TRNG components due to its features like ultra low power dissipation, low area and ultra high operating frequency. The proposed TRNG is comprised of self starved feedback circuit and floating clock generator. Again, the basis of self starved feedback circuit is a single bit QCA SRAM cell, which extracts the random digital bit. Furthermore, to enhance the randomness, floating clock generator is implemented across self starved feedback circuits input. The functionality of proposed TRNG is accomplished through QCA Designer tool and its architecture is also passed NIST statistical test of randomness. Hence proposed 8 bit TRNG can be interpreted as a novel contender for security applications due to its 14.82 GHz operating frequency, 0.36 μm2 area, latency of 1 QCA clock cycle, 28.53 meV average power dissipation and high tail probability of NIST test battery report in QCA technology.

A 0.2-V Three-Winding Transformer-Based DCO in 16-nm FinFET CMOS

Abstract: In this brief, we introduce a 3.2–4 GHz three-winding transformer-based class-F digitally controlled oscillator (DCO) with a DC-DC booster for energy harvesting applications. A $\pi $ -model is adopted for this multi-turn transformer to analyze its impedance transformation and overall loop gain. The trifilar coil generates large passive voltage loop gain, allowing the DCO supply voltage of 0.2 V to be even lower than the threshold voltage of transistors without any performance degradation. Due to the gate/drain isolation as well as smaller voltage-dependent capacitance in advanced FinFET technology, this brief achieves very low supply frequency pushing of 38 MHz/V. The switched capacitor placed at the tertiary winding can reach very fine resolution of 1.3 kHz due to the impedance transformations and source degeneration. The bias and control voltages of nearly zero power are generated with a switched-capacitor based DC-DC converter and a ring-based non-overlapped clock generator.

Dual-Mode RFID Tag IC Supporting Gen-2 and Visible RFID Modes Using a Process-Compensating Self-Calibrating Clock Generator

Abstract: An ultrahigh-frequency (UHF) band passive radio-frequency identification (RFID) tag integrated circuit (IC) supporting both generation-2 (Gen-2) and visible RFID modes is proposed in this paper. Two sources can be used to provide modulated data for the dual-mode tag IC: a radio frequency (RF) or visible light (VL) source. When a modulated RF signal is used, the tag IC operates in electronic product code Gen-2 mode. In the visible RFID mode, modulated VL delivers data and continuous-wave RF provides power for the tag IC. In both modes, power is provided by RF. For the tag IC, a self-calibrating clock generator (CLKG) robust to process variation is proposed. Without a battery, the CLKG has an accuracy of ±4% by continuously calibrating its frequency using downlink pulse-interval encoding (PIE) symbols from a reader. In the core of the CLKG, there is a new PIE decoder that reliably distinguishes between data-0 and data-1 under process, voltage, and temperature variations. The tag IC has been fabricated using a 0.18 μm CMOS process with a chip area of 1.4 × 1.7 mm2. The power consumption of the tag IC is 64 μW. Experiments are conducted using a photodiode in the visible RFID mode. With 0.34 mW power from a VL source, the tag IC shows successful detection of VL signal at distances up to 15 m.

High-frequency exciton-polariton clock generator

Abstract: Integrated circuits of photonic components are the goal of applied polaritonics. Here, we propose a compact clock generator based on an exciton-polariton micropillar, providing optical signal with modulation frequency up to 100 GHz. This generator can be used for driving polariton devices. The clock frequency can be controlled by the driving laser frequency. The device also features low power consumption (1 pJ/pulse).

A 580 nW Dual-Input Energy Harvester IC Using Multi-Task MPPT and a Current Boost Converter for Heterogeneous Source Combining

Abstract: Herein, we present a multi-energy harvesting interface integrated circuit (IC) that enables the efficient combination of heterogeneous power sources. An electromagnetic vibration energy generator (EVG) and a thermoelectric energy generator (TEG) are the two energy sources, which have quite different internal resistance (tens and kilo-Ohms). To solve the challenge of combining heterogeneous sources, we propose a current boost converter (CBC), which achieves the resistance transformation as well as the source type conversion. The challenge of realizing maximum power point tracking (MPPT) for each source is tackled by using a multi-task MPPT controller, which is efficiently shared between the two sources. To achieve energy harvesting under uncertain and random source conditions, we propose an input ( $V_{\text {IN}}$ )-dependent clock generator (VCG) and a vibration pulse detector (VPD). The VCG tracks the change of source conditions to generate the clock for the MPPT controller. The VPD allows tracking of the random amplitude and frequency changes of the EVG. The energy harvester is fabricated in a 0.18 $\mu \text{m}$ process with a thick top-metal option. Measured results show successful source detection, switching, and MPPT operation. The proposed IC provides an output power of up to 119 $\mu \text{W}$ with an end-to-end peak efficiency of 82% by consuming 582 nW.

A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based Multiphase Clock Generator

Abstract: This article presents a four-level pulse-amplitude modulation (PAM4) quarter-rate clock and data recovery circuit (CDR). A quarter-rate linear phase detector (QLPD) is proposed to reduce the recovered clock jitter by removing the dithering jitter of the bang-bang PD. A self-biased phase-locked loop (PLL)-based multiphase clock generator (MCG) with a very wide loop bandwidth (around 600 MHz) is proposed to reduce the MCG power consumption and generate a low-jitter multiphase clock for the quarter-rate operation. Fabricated in a 40-nm CMOS process, the prototype achieves a bit efficiency of 0.46 pJ/bit at 32-Gb/s input data rate. The measured jitter tolerance (JTOL) at the bit error rate (BER) of < 10−12 is higher than 0.35 UIPP with the corner frequency at about 10 MHz. The measured integrated jitter of the 4-GHz recovered clock is 352.6 fs.

A DLL-Based Quadrature Clock Generator With a 3-Stage Quad Delay Unit Using the Sub-Range Phase Interpolator for Low-Jitter and High-Phase Accuracy DRAM Applications

Abstract: In an effort to keep pace with bandwidth growth, DRAM employes the quad data rate (QDR) to transfer four data in one clock cycle. In recent graphic memories, QDR is being implemented by a phase-locked loop (PLL). However, it is hard to apply a PLL to main and mobile memories for its high power dissipation and hardware cost. Therefore, we propose a new delay-locked loop-based quadrature clock generator (DLL-QCG) to replace a PLL. A sub-range technique is adopted for a phase interpolator (PI) to achieve a very fine resolution with low power and small area. A tiny resolution mitigates the jitter accumulation effect of the conventional all-digital DLL-QCG and reduces a phase error. With the introduction of the sub-range PI, the delay line structure is changed from two-stage (coarse-fine) to three-stage (coarse-fine-finer). To control this, we also develop a new controller, which ensures clock quality through seamless boundary switching at the fine-to-finer. The circuit is fabricated using a 28 nm CMOS FDSOI technology with a 1 V supply voltage and an area of 0.0072 mm2. It operates from 1.8 to 2.5 GHz and achieves a phase error of 3.35° to 6.35° without a quadrature-phase collector. In addition, the measured RMS and peak-to-peak jitters at operating bandwidth are 1.05 to 1.71 ps and 8.4 to 12 ps, respectively.

Optical receiver, optical transmitter, data identification method, and multilevel communication system

Abstract: An optical receiver to receive a multilevel modulation signal in which a value of transmission data is assigned to plural signal levels, the optical receiver including a clock generator to generate a recovered clock signal from the multilevel modulation signal when the clock generator detects that a signal level of the multilevel modulation signal transitions between two median levels of the signal levels, and a data identifier to identify a value of the transmission data by using the generated recovered clock signal and the multilevel modulation signal.

A 6 GHz 130 nm CMOS Harmonic Recombination RF Receiver Front-End Using N-Path Filtering

Abstract: An RF receiver front-end using two feedforward N-path switching filters and harmonic-recombination configuration is presented. As the time-variant nature of the N-path filter introduces multiple frequency translations, third harmonic selection of the switching frequency rather than the fundamental helps to reduce the input frequency of the multiphase clock generator by a factor of three. The proposed 5.9-7.1 GHz RF receiver operates at the third harmonic of the local oscillator, thanks to the combination of an N-Path switching filter and a harmonic recombination architecture. The receiver is implemented in a 130 nm CMOS technology and operates from a 1.2 V supply. Post-layout simulation results show that, for a 6 GHz RF input, the receiver provides a harmonic rejection of 45 and 55 dB for the first and second harmonics, respectively. A noise figure of 5.5 dB at a 16 MHz baseband frequency is achieved, and an input matching of less than -15 dB is attained over the desired frequency band.

A low power and low ripple CMOS high voltage generator for RFID transponder EEPROM

Abstract: A high-voltage generator (HVG) is an essential part of a radio frequency identification electrically erasable programmable read-only memory (RFID-EEPROM). An HVG circuit is used to generate a regulated output voltage that is higher than the power supply voltage. However, the performance of the HVG is affected owing to the high-power dissipation, high-ripple voltage and low-pumping efficiency. Therefore, a regulator circuit consists of a voltage divider, comparator and a voltage reference, which are respectively required to reduce the ripple voltage, increase pumping efficiency and decrease the power dissipation of the HVG. Conversely, a clock driving circuit consists of the current-starved ring oscillator (CSRO), and the non- overlapping clock generator is required to drive the clock signals of the HVG circuit. In this study, the Mentor Graphics EldoSpice software package is used to design and simulate the HVG circuitry. The results showed that the designed CSRO dissipated only 4.9 μW at 10.2 MHz and that the phase noise was only -119.38 dBc/Hz at 1 MHz. Moreover, the proposed charge pump circuit was able to generate a maximum VPP of 13.53 V and it dissipated a power of only 31.01 μW for an input voltage VDD of 1.8 V. After integrating all the HVG modules, the results showed that the regulated HVG circuit was also able to generate a higher VPP of 14.59 V, while the total power dissipated was only 0.12 mW with a chip area of 0.044 mm2. Moreover, the HVG circuit produced a pumping efficiency of 90% and reduced the ripple voltage to <4 mV. Therefore, the integration of all the proposed modules in HVG ensured low-ripple programming voltages, higher pumping efficiency, and EEPROMs with lower power dissipation, and can be extensively used in low-power applications, such as in non-volatile memory, radiofrequency identification transponders, on-chip direct current DC-DC converters.

Methods and systems for performing decoding in finFET based memories

Abstract: A fin-Field Effect Transistor based system on chip (SoC) memory is provided and includes a control block, first logic gates, and row decoder blocks. The control block includes a clock generator circuit that generates an internal clock signal, and a global driver circuit coupled to the clock generator circuit that drives a global clock signal. Each row decoder block includes a second logic gate that receives higher order non-clocked address signals via input terminals, a transmission gate that combines the global clock signal and the higher order non-clocked address signals, third logic gates that receive lower order non-clocked address signals and higher order clocked address signals, and output a combined lower order address and higher order address along with the global clock signal, level shifter circuits that receive the outputs, and word-line driver circuits that generate word-lines based on the output of the level shifter circuits.

An Adaptive Clock Scheme Exploiting Instruction-Based Dynamic Timing Slack for a GPGPU Architecture

Abstract: This article presents an adaptive clock scheme to exploit instruction-based dynamic timing slack (DTS) for a general-purpose graphics processor unit (GPGPU) architecture. Based on the developed transitional static timing analysis, the deterministic DTS can be identified for each instruction at different pipeline stages. A critical path (CP) messenger scheme was designed to monitor the runtime utilization of CPs. Both real-time issued instruction information and CP messengers are utilized to determine the runtime DTS margin and guide the cycle-by-cycle clock period adjustment. To apply the proposed adaptive clock on GPGPU, a hierarchical clocking scheme is built including a global phase-locked loop (PLL) and local delay-locked loop (DLL)-based clock generator inside each compute unit (CU). Each CU core contains its own clock domain with adjustable local clocking. In addition, to exploit error-resilient characteristics of the neural network, an elastic pipeline clocking scheme is developed to redistribute the timing margin across pipeline stages for machine learning computations. Measurement results from the implemented open-source GPGPU architecture on a 65 nm CMOS process demonstrate up to 18% performance improvement or equivalent 30% energy saving can be obtained by exploiting the deterministic instruction-based DTS. The proposed elastic pipeline clocking can gain an additional 8% energy saving with small accuracy degradation for neural network inference operations.

Design and Analysis of Clock Fault Injection for AES

Abstract: Traditional cryptography security often relies on the security of the cryptographic algorithm itself. However, in practice, cryptographic algorithms are always implemented based on software or hardware. In fault attack, attackers induce errors during encryption calculations to extract key information in embedded systems. Clock glitch injection poses a serious threat to cryptographic algorithms, which is a kind of fault attack. This paper proposes a built-in faulty clock generator integrated on FPGA to evaluate fault injection attacks and their impact on encryption modules. The platform generates glitches in a normal clock cycle, and can change the influence range of clock failures by accurately controlling the position and shape of the glitches. The research in this paper shows that the glitch can appear in any assigned cycle, and the width can be adjusted with increments of 0.14ns when the clock cycle is 20ns. This platform has great significance and value for standardizing the failure evaluation process of resource-constrained cryptosystems and building a unified security evaluation framework.

A 32-Step Phase-Compensated Spread-Spectrum RF-PLL With 19.44-dB EMI Reduction and 10-fs Extra RMS Jitter

Abstract: Spread-spectrum clocking (SSC) is an active solution to attenuate electromagnetic interference (EMI) in Gb/s serial communication systems by slightly modulating the phase-locked loop (PLL) output clock frequency. This article presents a phase-compensated spread-spectrum clock generator (SSCG) with the state-of-the-art EMI reduction and clock rms jitter performance. A 32-slice scaled resistor-based buffer is proposed to realize the phase interpolator (PI). The proposed design has no static current and low complexity without active device matching requirement. The 32-slice PI structure can achieve a simulated 22-dB EMI reduction with a 32-step triangular modulation profile. The proposed SSCG chip with a charge-pump-based fractional- $N$ radio frequency (RF)-PLL and a source-series-terminated (SST) driver is fabricated using a 55-nm CMOS process. Measurement result shows that EMI reduction of the 5-GHz output clock power spectrum is 19.44 dB under 0.5% down-spread. The rms jitters with SSC-off and SSC-on, adopting a second-order clock recovery in oscilloscope, are 630 and 640 fs, respectively. The normalized power consumption is 9.3 mW/GHz, and the core area occupation is 0.092 mm2.

A 1.45 GHz All-Digital Spread Spectrum Clock Generator in 65nm CMOS for Synchronization-Free SoC Applications

Abstract: The increase of clock frequency in digital circuits exacerbates the electromagnetic interference (EMI) between devices. Spread-spectrum techniques reduce the electromagnetic noise lowering harmonic peaks of the clock signal by means of frequency modulation. In System-on-Chips (SoCs) another requirement in many applications is the coexistence of both modulated and un-modulated clock domains. In these cases, suitable synchronization systems are used to allow data to cross the boundary between spread and un-spread clock domains. In this paper we present a spread-spectrum clock generator (SSCG) able to provide both spreaded and un-spreaded clocks. The spreaded clock has a specially designed modulation profile, allowing at the same time a seamless synchronization-free interface between spreaded and un-spreaded clock domains and a large EMI reduction. The paper presents the derivation of the new highly discontinuous modulation profile (that allows to achieve an EMI reduction up to 15.8dB) and implementation details of an all-digital SSCG able to provide the developed modulation waveform. A test chip has been fabricated in UMC 65nm CMOS technology, using a novel dual-output digitally controlled delay line. The circuit can generate both spread and un-spread clocks (double output mode) or the spread clock alone (single output mode). Area occupation is 0.102mm2, whereas power consumption is 48.5mW in double output mode and 34mW in single output mode.

A Broadband CMOS Pulse Generator for UWB Systems

Abstract: A broadband pulse generator (PG) for ultra-wideband (UWB) systems, which includes a Gaussian pulse generator, 5 double balanced (DB) Gilbert-cell up-converter mixers, an analog adder, and an LO clock generator unit, respectively, was fabricated in 65 nm CMOS. Measurement shows that generated dc-free multi-tone pulse has a flat spectrum and linear phase change within 1 GHz bandwidth, with a peak-to-peak amplitude of 280 mV and linear phase change. The die area is only 0.082 mm2 and power consumption is ∼4.5 mW from a 1 V supply.

Semiconductor device performing refresh operation in deep sleep mode

Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of memory cells, a first counter circuit configured to periodically update a count value during a first operation mode, a burst clock generator configured to successively generate a burst pulse predetermined times when the count value indicates a predetermined value, and a row address control circuit configured to perform a refresh operation on the memory cell array in response to the burst pulse.

Fine-grained clock resolution using low and high frequency clock sources in a low-power system

Abstract: A periodic output generator has a first clock source coupled to a first counter and a second clock source with a frequency greater than the first clock source, the second clock source coupled to a second counter, the first clock source operating continuously, the second clock source enabled when the first clock source reaches a count C1. The second clock source generates an output when a count C2 is reached, and the counters are reset and the process repeats. In another example, a timestamp generator has a high speed clock and a real time clock operative on a low speed clock. The timestamp generator receives an external event, turns on the high speed clock generator and counts high speed clock cycles C until the arrival of the next time stamp, and computes an event timestamp as the next timestamp less c/f, less the startup time of the high speed clock.

A 48 Gb/s PAM-4 Transmitter With 3-Tap FFE Based on Double-Shielded Coplanar Waveguide in 65-nm CMOS

Abstract: A power and area-efficient pulse-amplitude modulation 4 (PAM-4) transmitter using 3-tap feed-forward equalizer (FFE) based on a slow-wave transmission line is presented. Passive delay line is adopted for generating equalizer tap to overcome the high clocking power consumption. The transmission line achieves high slow-wave factor of 15 with double floating metal shields around the differential coplanar waveguide. The physical dimensions of the transmission line are determined to have low loss and a high slow-wave factor with a small chip area by optimization with 3-D electromagnetic simulations. The transmitter includes 4:1 multiplexers (MUXs) and a quadrature clock generator for high-speed data generation in a quarter-rate system. The 4:1 MUX utilizes 2-UI pulse generator and the input configuration is determined by qualitative analysis. The chip is fabricated in 65-nm CMOS technology and occupies area of 0.151 mm2. The proposed transmitter system exhibits the energy efficiency of 3.03 pJ/b at the data rate of 48 Gb/s with PAM-4 signaling.

An N-Path Filter Design Methodology With Harmonic Rejection, Power Reduction, Foldback Elimination, and Spectrum Shaping

Abstract: In this paper, an adaptive design methodology for synthesizing a harmonic free N-path filter with reduced frequency folding is presented. System level analysis of proposed architecture shows that by adding a few extra paths with proper weights to a conventional N-path filter, several characteristics such as harmonic rejection, power reduction, foldback elimination and spectrum shaping can be achieved. The designed filter is reconfigurable to be a band-pass filter (BPF) or a band-reject filter (notch), based on the requirements. By using the nth harmonic of Local Oscillator (LO) signal, instead of the fundamental harmonic, the required input clock frequency in N-phase clock generator is reduced by a factor of ${n}$ . As a proof of concept, a 0.1-5 GHz RF filter with 75 dB and 82 dB harmonic rejection at 3rd and 5th order harmonics respectively is analyzed and simulated using MATLAB and Cadence Spectre-RF. Post-layout simulations are performed using CMOS 180 nm technology with 1.8 V supply voltage. The total power consumption of the chip is less than 8.5 mW while occupying a silicon area of 0.2 mm2. Furthermore, Noise Figure (NF) of the circuit is shown to be between 3.5 and 4.7 dB and its out-of-band IIP3 is +6 dBm.

CMOS analog and mixed-signal phase-locked loops: An overview

Abstract: CMOS analog and mixed-signal phase-locked loops (PLL) are widely used in varies of the system-on-chips (SoC) as the clock generator or frequency synthesizer. This paper presents an overview of the AMS-PLL, including: 1) a brief introduction of the basics of the charge-pump based PLL, which is the most widely used AMS-PLL architecture due to its simplicity and robustness; 2) a summary of the design issues of the basic CPPLL architecture; 3) a systematic introduction of the techniques for the performance enhancement of the CPPLL; 4) a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter (< 100 fs) with lower power consumption compared with the CPPLL, including the injection-locked PLL (ILPLL), sub-sampling (SSPLL) and sampling PLL (SPLL); 5) a discussion about the consideration of the AMS-PLL architecture selection, which could help designers meet their performance requirements.

A 951-fs rms Period Jitter 3.2% Modulation Range in-Band Modulation Spread-Spectrum Clock Generator

Abstract: A spread-spectrum clock generator is proposed based on an in-band phase modulation. In a charge-pump phase-locked loop configuration, the input phase modulation signal is applied to the proposed charge-based discrete-time loop filter. The phase difference between the input phase modulation signal and the output clock feedback phase is sampled and applied to the control voltage of an oscillator. The loop gain of the clock generator pushes the output clock phase to accurately trace the input phase modulation signal. This article achieves 3.2% spread-spectrum modulation range and 26.51-dB spread-spectrum attenuation at 352-MHz output frequency using a 2-MHz reference frequency. The in-band modulation improves a design sensitivity, and a 298-ppm modulation range error is measured with over 140% $K_{\mathrm{ VCO}}$ perturbations. This spread-spectrum clock generator is implemented in a 0.18- $\mu \text{m}$ CMOS, and achieves 951-fsrms period jitter while consuming 9.98 mW from a 1.8-V power supply.

A 2.3 mW Multi-Frequency Clock Generator with −137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology

Abstract: A fast phase frequency detector (PFD) and low gain low phase noise voltage-controlled oscillator (VCO)-based phase-locked loop (PLL) design are presented in this paper. PLL works in the frequency r...

On-Chip Delay Measurement for Degradation Detection And Its Evaluation under Accelerated Life Test

Abstract: Periodical delay measurement in field is useful for not only detection of delay-related faults but also prediction of faults due to aging. Logic BIST with variable test clock generation enables on-chip delay measurement in field. This paper addresses a delay measurement scheme based on logic BIST and gives experiment results to observe aging phenomenon of test chips under accelerated life test. The measurement scheme consists of scan-based logic BIST, a variable test clock generator, and digital temperature and voltage sensors. The sensors are used to compensate measured delay values for temperature and voltage variations in field. Evaluation using SPICE simulation shows that the scheme can measure a circuit delay with resolution of 92 ps. The delay measurement scheme is also implemented on fabricated test chips with 180 nm CMOS technology and accelerated test is performed using ATE and burn-in equipment. Experimental results show that a circuit delay increased 552 ps when accelerated the chip for 3000 hours. It is confirmed that the on-chip delay measurement scheme has enough accuracy for detection of aging-induced delay increase.

A low power low ripple Schmitt trigger based PWM Boost Converter for Energy Harvesting Applications

Abstract: The design of monolithic power management circuits is critical in energy harvesting applications. A Pulse width modulation (PWM) boost converter with feedforward and feedback control mitigates the changes in input-output parameters and avoids the use of compensation circuit. However, the conventional design of a clock generator in feedback path employs power hungry comparators and latches. This paper proposes an improved design of clock generator replacing comparators and latches with a schmitt trigger circuit. As a result, a low power and a low ripple PWM was acheived. The design was implemented in UMC 180 nm CMOS technology generating a stable output of 3.3 V for an input range of 1.2 V - 1.6 V. Due to the application of the proposed technique, a reduced power consumption of 60.19 mW and low ripple voltage of 18.29 mV was achieved, for a maximum load current of 100 mA at an efficiency of 98%. Thus making the design suitable for energy harvesting applications.

Controller with limit control to change switching period or switching frequency of power converter and methods thereof

Abstract: A power converter controller includes a control loop clock generator that generates a switching frequency signal in response to a sense signal representative of a characteristic of the power converter, a load signal responsive to an output load, and a limit signal representative of a maximum length of a current half cycle of the switching frequency signal. A comparator generates an enable signal in response to the load signal and a load threshold. A limit control generates the limit signal in response to the enable signal and the switching frequency signal. A rate of change of half cycles of the switching frequency signal is controlled in response to the limit signal. A request transmitter generates a request signal in response to the switching frequency signal to control switching of a switching circuit coupled to the energy transfer element and an input of the power converter.

A DT-MOS switched-capacitor based step-up DC/DC converter for energy harvesting applications

Abstract: An ultra-low-power, subthreshold switched-capacitor based step-up DC/DC converter is proposed for energy harvesting applications. To enable for low voltage operation, a dynamic body biasing applying to both charge pump and non-overlapping clock generator. As a result, a significant drop in switching loss and leakage current accordingly improves the transient response of output voltage and pumping efficiency. A four-stage cross-coupled voltage doubler circuit is designed with both NMOS and PMOS transistors to provide direct charge flow. The proposed circuit has been implemented in CMOS 0.18 $\mu$m process. Simulation results describe a low start-up voltage of 400 mV with an output voltage of 1.93 V and pumping efficiency of 96.5% while the total circuit dissipates just 2.4 $\mu$W.

Gate clock generator and display device having the same

Abstract: The present disclosure provides a gate clock generator including a counter, a buffer control signal generator, and an output unit. The counter receives control data having rising timing information and falling timing information and a main clock. The counter generates a first output when a value is obtained by counting the main clock from a preset reference time point reaches rising data. The counter further generates a second output when a value is obtained by counting the main clock from the reference time point reaches falling data. The buffer control signal generator generates a first buffer control signal of a gate ON voltage from a timing of the first output to a timing of the second output. The output unit outputs a gate ON voltage of a gate clock during an output period of the gate ON voltage of the first buffer control signal.