Showing papers on "Clock synchronization published in 1999"

Synchronization process negotiation for computing devices

Abstract: A methodology providing “synchronization process negotiation” is described. Synchronization process negotiation is the methodology of negotiating between two or more devices exactly what synchronization process (protocol) is to be employed to effect synchronization of the devices. The methodology, which is adaptable to existing synchronization protocols, takes into account the actual synchronization capabilities or built-in support (if any) of each device whose data is to be synchronized (e.g., by a synchronization engine). The methodology may be implemented by adapting a given synchronization protocol (which itself may be one of a variety of types) to include a “negotiation phase” at the beginning of the synchronization, during which the devices involved will exchange information about the capabilities of one or more devices. The individual attributes for a client are communicated as synchronization parameters in attribute/value pair form. Once this negotiation phase has been completed, the synchronization can then proceed in a manner that is most efficient for the features available.

Plausible clocks: constant size logical clocks for distributed systems

Abstract: In a Distributed System with N sites, the precise detection of causal relationships between events can only be done with vector clocks of size N. This gives rise to scalability and efficiency problems for logical clocks that can be used to order events accurately. In this paper we propose a class of logical clocks called plausible clocks that can be implemented with a number of components not affected by the size of the system and yet they provide good ordering accuracy. We develop rules to combine plausible clocks to produce more accurate clocks. Several examples of plausible clocks and their combination are presented. Using a simulation model, we evaluate the performance of these clocks. We also present examples of applications where constant size clocks can be used.

Organization of time synchronization in a distributed system

Abstract: A distributed system with mechanisms for automatic selection of master and slave clocks to be used for clock synchronization. The distributed system includes a set of nodes (20-24), including a first node and a second node, each having a local clock (30-34) and a set of information (40-44) pertaining to the local clock (30-34). The first node transfers a packet (50) on a communication link (12) that carries the information (52). The second node receives the packet (50) on the communication link (12) and determines whether the local clock of the second node is a master clock that synchronizes a time value in the local clock of the first node or a slave clock that synchronizes to a time value from the local clock in the first node by comparing the information (52)in the packet (50)to the information pertaining to the local clock in the second node. Automatic selection of master and slave clocks in boundary nodes (92) is provided along with mechanisms for determining clock synchronization delays and mechanisms for reporting jitter associated with communication devices (14).

Wide capture range circuitry

Abstract: Circuitry and method for synchronizing operating speeds of signal processing devices to the data rate of a signal. It applies in particular to Compact Disk (CD) and Digital Versatile Disk (DVD) drives to be used with portable devices. The circuitry does not require clock synchronization speeds in excess of the instantaneous data rate used by the disk drive and also reduces power consumption.

Power system time synchronization device and method for sequence of event recording

Abstract: The invention relates to the field of power distribution systems and more particularly to power monitors within such a system. A time synchronization device and method for synchronizing an internal clock of the power monitor to a periodically stable frequency is provided. Cycles of the periodically stable frequency are counted after each elapse of a predetermined time period. The elapse of the predetermined time period defines a present window and a previous window. A counting error and a change in counting error are calculated, wherein the change in counting error is the difference of a counting error calculated for the present window and a counting error calculated for the previous window. The present method detects when a change in counting error is within a predetermined range. When the counting error is within the predetermined range, the internal clock of the power monitor is adjusted to the line frequency according to the counting error calculated for the present window.

Formal verification for time-triggered clock synchronization

Abstract: Distributed dependable real time systems crucially depend on fault tolerant clock synchronization. The paper reports on the formal analysis of the clock synchronization service provided as an integral feature by the Time-Triggered Protocol (TTP), a communication protocol particularly suitable for safety-critical control applications, such as in automotive "by-wire" systems. We describe the formal model extracted from the TTP specification and its formal verification, using the PVS system. Verification of the central clock synchronization properties is achieved by linking the TTP model of the synchronization algorithm to a generic derivation of the properties from abstract assumptions, essentially establishing the TTP algorithm as a concrete instance of the generic one by verifying that it satisfies the abstract assumptions. We also show how the TTP algorithm provides the clock synchronization that is required by a previously proposed general framework for verifying time-triggered algorithms.

Synchronization and cell search methods and apparatus for wireless communications

Abstract: A received communications signal is correlated with a common synchronization code to produce a synchronization detection signal. A component of the synchronization detection signal associated with a known synchronization signal is canceled from the synchronization detection signal to produce an interference-canceled synchronization detection signal. Timing of a synchronization signal is determined from the interference-canceled synchronization detection signal. According to one aspect, interference cancellation is achieved by generating a correlation of an estimated received known synchronization signal with the common synchronization code, canceling the correlation of the estimated received known synchronization signal with the common synchronization code from the synchronization detection signal to produce the interference-canceled synchronization detection signal. Timing of a synchronization signal may then be determined by accumulating the interference-canceled synchronization detection signal over a time interval, detecting a peak in the accumulated interference-canceled synchronization detection signal, and determining timing of a synchronization signal from the detected peak. According to another aspect, interference cancellation is achieved by accumulating the synchronization detection signal over a time interval, identifying a peak in the accumulated synchronization detection signal not associated with a known synchronization signal, and determining timing of a synchronization signal from the identified peak. Related terminal apparatus are also discussed.

Optimal and efficient clock synchronization under drifting clocks

Abstract: We consider the classical problem of clock synchronization in distributed systems. Previously, this problem was solved optimally and efficiently only in the case when all individual clocks are non-drifting, i.e., only for systems where all clocks advance at the rate of real time. In this paper, we present a new algorithm for systems with drifting clocks, which is the first optimal algorithm to solve the problem efficiently: clock drift bounds and message latency bounds may be arbitrary; the computational complexity depends on the communication pattern of the system in a way which is bounded by a polynomial in the network size for most systems. More specifically, the complexity is polynomial in the maximal number of messages known to be sent but not received, the relative system speed, and time-stamp size. Our result has two consequences. From the theoretical standpoint, it refines the known bounds for optimal synchronization. But even more importantly, it enables us to derive new optimal algorithms that are reasonably efficient for most practical systems.

Method and apparatus for audio and video end-to-end synchronization

Abstract: A method and apparatus for synchronization of an audio/visual bitstream is transmitted by an encoder and received by a decoder by employing duplication or elimination of audio samples and video pixels. The invention enables clock synchronization between the encoder and a decoder with an unregulated clock oscillator so as to control the data reader by skipping ahead (eliminating a data element) or to pause (duplicating a data element) depending on whether the encoder clock is faster or slower than the decoder clock.

Network clock synchronization scheme

Abstract: A clock distribution tree for a digital network is automatically established through the use of spanning tree computations at nodes of the network. The computations rely, at least in part, upon the exchange of clock distribution messages between the nodes of the network. Each clock distribution message includes information regarding a clock source available at the source node of the message. The clock distribution tree is hierarchical in nature, with nodes that are lower in the hierarchy (i.e., at a higher stratum level) extracting clock from links with nodes that are higher in the hierarchy (i.e., at a lower stratum level); this helps preserve the synchronous digital hierarchy of the network. The spanning tree computations involve a root selection process and a convergence test. The root selection process is made on the basis of configuration vectors exchanged as part of the clock distribution messages. The configuration vectors include a port priority, a node stratum level and a primary reference source identifier. The convergence test includes determining whether a number of clock distribution messages received or transmitted equals a network maximum diameter parameter for the network.

Remote synchronization with intelligent power management

Abstract: Synchronization techniques that improve the ease with which synchronization operations can be performed are disclosed. Synchronization is performed between resources on a portable computing device and resources stored on a remote server. The synchronization can be centralized across different types so that user interaction to achieve the different types of synchronization is minimal. Battery power can also be conserved during synchronization. A user can also be informed as to when the portable computing device should be shut-down or placed in a low-power state to have sufficient battery power remaining to perform the synchronization. The synchronization operations can be easily activated without much user interaction.

Experience with an adaptive globally-synchronizing clock algorithm

Abstract: Fast commodity network-connected PC or workstation clusters are becoming more and more popular. This popularity can be attributed to their ability to provide highperformance parallel computing on a relatively inexpensive platform. An accurate global clock is invaluable for these systems, both for measuring network performance and coordinating distributed applications. Typically, however, these systems do not include dedicated clock synchronization sup port. Previous clock synchronization methods are not suitable here in general, either because of extra, non-commodity hardware requirements or insufficient synchronized clock accuracy. In this paper we present and evaluate an adaptive clock synchronization algorithm. We have implemented and tested the algorithm on our Myrinet-based PC cluster. It is regularly used as part of a parallel performance tool running on the cluster. The algorithm has several important features. First, it does not require any extra hardware support. Second, we show that this algorithm imposes very low overhead on the system and has microsecond-level accuracy. Finally, our results indicate that adding the ability to adaptively adjust the clock’s re-synchronization period causes almost no extra overhead while achieving a much better global clock accuracy.

Fail-aware datagram service

Abstract: In timed asynchronous distributed systems, it is often useful for a process p to know that another process q will not use a certain piece of information p has sent to q beyond a certain deadline. Since p learns about the occurrence of the deadline by simply measuring the passage of time on its own local clock, we call this kind of interprocess communication “communication by time”. Knowledge of computed upper bounds on one-way message transmission delays is a necessary prerequisite for this kind of communication.

A dejittering and clock recovery technique for real-time audio/visual network applications

Abstract: In a real-time audio/visual system in which A/V data is conveyed over a jitter-introducing network, dejittering and clock recovery processes can be achieved without requiring a Phase Locked Loop (PLL). At the server, audio/video streams are encoded into transport packets before being sent out. At the client, the dejittering process is achieved by a dejittering buffer using the embedded timestamps in the transport packets and a client decoding clock. The delay variations of data arriving are removed after the client buffering process. At the scheduled time, each data packet is shifted to a synchronizing buffer and then fed to the A/V decoder according to the speed of A/V stream. The clock synchronization between client and server is achieved by a synchronizing buffer whose half-size position is taken as the reference. By monitoring the movement of the buffer fill position over a given period, the drift rate of clock unsynchronization between client and server can be derived and, therefore, the client's clock can be adjusted to synchronize with the server's clock based on the derived drift.

Towards systematic testing of distributed real-time systems

Abstract: Reproducible and deterministic testing of sequential programs can in most cases be achieved by controlling the sequence of inputs to the program. The behavior of a distributed real-time system, on the other hand not only depends on the inputs but also on the order and timing of the concurrent tasks that execute and communicate with each other and the environment. Hence, sequential test techniques are not directly applicable, since they disregard the significance of order and timing of the tasks. In this paper we present a method for identifying all possible orderings of task starts, preemptions and completions for tasks executing in a distributed real-time system. Together with an accompanying testing strategy, this method allows test methods for sequential programs to be applied, since each identified ordering can be regarded as a sequential program. In the presented analysis and testing strategy, we consider task sets with recurring release patterns, and take into account the effects of clock synchronization and variations in start and execution times of the involved tasks.

Power Control in Cellular Radio Systems : Analysis and Design

Abstract: Many algorithms in communications systems can be considered as control loops, where the computed quantities depend on feedback information. A common scheme is to use increase/decrease signaling for bandwidth efficiency. Furthermore, the feedback information is delayed. The time delay itself, and even more pronounced in combination with nonlinearities, such as the increase/decrease mechanism, may cause oscillations and instabilities in the system. In this work, analysis methods based on root locus and describing functions are discussed. Design and tuning of algorithms are employed using pole placement techniques. Particular examples include clock synchronization in ADSL modems, control of available bit rate in data networks and, as studied in this project, distributed implementation of power control in cellular radio systems. The relevance of the methods is further illuminated by simulations.

Fast re-synchronization of independent domain clocks after powerdown to enable fast system start-up

Abstract: A system having several clock domains must have domain clocks properly aligned before powering up from a low-power or power-down mode. The domain clocks can be quickly aligned to enable fast system start-up if the clocks are forced into a rough alignment before a fine alignment process begins. Initially, a phase offset between the domain clocks is determined using a sync pulse, which indicates a location of one of the domain clocks relative to the other domain clock. Next, the domain clocks are forced into a minimum phase offset configuration by phase stalling one of the domain clocks. The phase stalling includes adjusting the pulse width of one of the domain clocks to force the clock into a rough alignment with the other domain clock. Finally, the domain clocks are fine aligned, and the system is placed into a normal power mode.

Universal synchronization clock signal derived using single forward and reverse direction clock signals even when phase delay between both signals is greater than one cycle

Abstract: A synchronous bus system includes a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices. The forward direction clock segment carries a forward direction clock signal, and the reverse direction clock segment carries a reverse direction clock signal. Synchronization clock circuitry, provided in each device, receives the forward direction clock signal and the reverse direction clock signal. Using the received clock signals, the synchronization clock circuitry derives a universal synchronization clock signal which is synchronous throughout all devices. Skew correction circuitry, provided in at least a portion of the devices, corrects for skew between the universal synchronization clock signal and one or more data signals for transferring data between devices.

Fault injection based on a partial view of the global state of a distributed system

Abstract: This paper describes the basis for and preliminary implementation of a new fault injector, called Loki, developed specifically for distributed systems. Loki addresses issues related to injecting correlated faults in distributed systems. In Loki, fault injection is performed based on a partial view of the global state of an application. In particular, facilities are provided to pass user-specified state information between nodes to provide a partial view of the global state in order to try to inject complex faults successfully. A post-runtime analysis, using an off-line clock synchronization and a bounding technique, is used to place events and injections on a single global time-line and determine whether the intended faults were properly injected. Finally, observations containing successful fault injections are used to estimate specified dependability measures. In addition to describing the details of our new approach, we present experimental results obtained from a preliminary implementation in order to illustrate Loki's ability to inject complex faults predictably.

Cycle independent data to echo clock tracking circuit

Abstract: A comparator and variable delay circuit are provided to maintain the tracking between data and echo clocks in a double data rate (DDR)RAM device. This is accomplished by providing a global data signal (dummy data signal) that tracks with the actual memory array data. This global data signal is compared to the timing of the RAM clock (CLOCK) to determine a delay time between the two by which the pipeline clocks (CLKRISE/CLKFALL) must be delayed. As a result, the pipeline clocks are pushed out as needed so that they always transition after the array data arrives at the output latch. Therefore, as cycle time decreases, both echo clocks and data are pushed out identically and maintain their required tracking.

Master-slave synchronization

Abstract: The invention relates to synchronization of network elements in a network that uses master-slave synchronization. The use of the known monitoring bit MCB (Master Clock Bit) is expanded in the method so that it is transmitted all the way from the master network element, for example the mobile switching center (MSC). If one of the network elements located between the master network element and a specific slave network element, for example a base station, does not accept the received signal as the synchronization source because of its quality, the network element in question forces the MCB bit located in the signal that the element transmits further to state 1. If the transmission unit of a specific slave network element is locked to the signal which includes the MCB in state 1, or if the element is forced to revert to using the internal clock because of a fault situation of the signal, the transmission unit activates the alert. Before the start of and during the synchronization of the base station clock, the fault status is read from the transmission unit and the synchronization is prevented or interrupted if the alert is on. The alert is given to other units of the base station in question from which the fault monitoring unit further transmits it through a separate operations and maintenance network to the operations center of the network operator.

Multinode computer system with distributed clock synchronization system

Abstract: A multinode multiprocessor computer system with distributed local clocks wherein a local clock may be synchronized with other clocks in the system without affecting the operation of the other clocks. A local clock to be synchronized is reset and counts an elapsed time since the reset. Simultaneously with resetting the local clock, a clock value from a clock on a source node is stored. The clock value from the source node is copied to the node to be synchronized and added to the elapsed time. The resulting summation is then stored in the local clock to be synchronized. As a result, the local clock is synchronized to the clock on the source node. In one system embodiment, the local clock includes a dynamic register and a base register and an adder adds the two portions together to generate an output of the local clock. For a node being synchronized, the dynamic portion is reset and allowed to count the elapsed time while the base portion is loaded with a clock value copied from the source node. In another system embodiment, a clock register stores both dynamic and base portions. For a node being synchronized, the clock register is reset and allowed to count the elapsed time. The base portion from the source node is then added to the clock register and stored in the clock register.

110 GB/s simultaneous bi-directional transceiver logic synchronized with a system clock

Abstract: Simultaneous bi-directional transceiver logic (SBTL) doubles data bandwidth because data are transmitted simultaneously in each direction over one wire. The technique has enhanced the cost performance of a commercial high-end UNIX server because the number of LSI signal pins, board signal nets, and connectors have decreased by half. And the SBTL speed can improve to more than 1 Gb/s per pin by using advanced process and circuit technology. The previous high frequency interface uses source-synchronous transmission. But a transmission that is not synchronized with a system clock requires long latency time of several cycles for clock synchronization and data recognition at the receiver LSI. A large interface circuit for the clock synchronization is a disadvantage. Therefore, the SBTL technique synchronized with a system clock has been developed in this work to minimize the latency time even at a high frequency of 1.1 Gb/s per pin. Also, a high-speed signal pin count per LSI is important. Low-noise technique of an output buffer circuit and a package has been developed to get a 100 B high-speed data bus per LSI. The maximum data bandwidth is 110 GB/s per LSI.

An algorithm for fault-tolerant clock state & rate synchronization

Abstract: We propose a fault-tolerant algorithm for synchronizing both state and rate of clocks in a distributed system. This algorithm is based on rounds, uses our fault-tolerant optimal precision (OF) convergence function as the means of synchronization, and maintains a collection of intervals to keep track of real-time, internal global time, and clock rates. The analysis shows that the interlocking between state and rate synchronization can be easily solved, and that oscillator stabilities together with the transmission delay uncertainties of packets predominate the internal synchronization. In addition, average case results gathered from simulation experiments with our SimUTC toolkit prove to be about one order of magnitude better than the worst case ones from the analysis of our state & rate algorithm.

Method and system for synchronizing multiple subsystems using one voltage-controlled oscillator

Abstract: A method for synchronizing multiple subsystems using one voltage-controlled oscillator. The method includes transmitting a phase and frequency aligned output of a voltage-controlled oscillator to each subsystem within a digital system. A first subsystem of the multiple subsystems generates a first internal clock and outputs a synchronization signal to each of the other subsystems. The synchronization signal has a marker that defines a known point in time of the first internal clock. The other subsystems sample the synchronization signal using the output signal of the voltage controller oscillator to determine a starting indicator that indicates the known point in time of the first internal clock. Upon detection of the marker in the synchronization signal, the other subsystems starts a second internal clock that is synchronized with the first internal clock.

Wireless network with clock synchronization

Abstract: The invention relates to a wireless network with a plurality of network nodes, each of which consists of at least one electrical apparatus and at least one radio device which are arranged to exchange data via a wireless medium. A network node includes a clock supply for supplying all electrical apparatus and the radio device with its clock. A network node which is designated as a main network node transmits, via its radio device, a synchronization pattern which is dependent on the clock of its clock supply. All other network nodes, referred to as secondary network nodes, are assigned to different, hierarchically ordered distance classes in dependence on their distance from the main network node which is assigned to the highest distance class. All secondary network nodes of a distance class transmit, via their respective radio device, a synchronization pattern which is dependent on the clock of their respective clock supply and characterizes the distance class. A secondary network node synchronizes its clock supply by means of at least one received synchronization pattern of a hierarchically higher distance class.

Cascading PLL units for achieving rapid synchronization between digital communications systems

Abstract: A clock synchronization system for synchronizing a first communications device and a second communications device to enable digital communication there between. A first device generates a first clock signal Fa. A second device generates a second clock signal Fb 2 . The second device includes a first PLL circuit and a second PLL circuit. The first PLL circuit is adapted to increase Fa by a factor K to produce a signal Fak. The second PLL circuit is adapted to increase Fak by a factor L to produce a signal Fbn. The second PLL circuit is further adapted to decrease Fbn by a factor N to produce the signal Fb 2 . The first PLL circuit and the second PLL circuit are adapted to adjust the values of K, L, and N such that a frequency lock is achieved between Fa and Fb 2 . enabling digital communication between the first device and the second device without requiring a predetermined phase lock between Fa and Fb 2.

Ultra-fast clock recovery for burst-mode optical packet communication

Abstract: A burst-mode clock recovery circuit design and its module for 10-Gbit/s optical packet communications are presented. A fabricated one-chip module required only 4 ns for clock synchronization. We also describe a burst-mode clock and data recovery experiment at a clock speed of STM64.

Ip terminal device, method for estimating frequency error range, method of estimating frequency difference and method of calculating estimated required time

Abstract: PROBLEM TO BE SOLVED: To solve the problem where the time during which synchronous control is completed cannot be predicted due to frequency difference being controlled without its being ascertained. SOLUTION: This IP terminal device provided with a synchronization function, which receives a synchronous timing packet transmitted by anther IP terminal device in a fixed interval and makes an internally generated clock synchronize with the clock of a transmitting side, is provided with the following means. The IP terminal device is provided with a clock generating means for generating an internal clock (1), a clock counter for counting the internal clock generated by the clock generating means (2), and a control means which estimates the frequency difference between the transmitting side clock and the clock generated by the clock generating means, on the basis of the finite difference between the count value of a clock counter when the first received synchronous timing packet after communication start is received and the count value of the counter clock, when a synchronous timing packet received after that is received and performs phase shift control of the clock generating means according to the estimation results. COPYRIGHT: (C)2001,JPO