Showing papers on "Contact resistance published in 1987"

Effects of interfacial microstructure on uniformity and thermal stability of AuNiGe ohmic contact to n-type GaAs

Abstract: As part of the investigation of the use of AuNiGe as the ohmic contact to n‐type GaAs at a high integration level, cross‐sectional transmission electron microscopy was used to explore the uniformity at the metal/GaAs interface and the thermal stability of the AuNiGe contact after the ohmic contact formation. A close relation between spread of the contact resistance and nonuniformity of the interfacial microstructure of the contact was found. Deposition of 5‐nm‐thick Ni as the first layer of the AuNiGe ohmic contact significantly reduced the spread of the contact resistance and led to the formation of a uniform interface without large protrusions. The improvement in uniformity of compound distribution and the reduction of interface roughness are believed to be due to a change in the sequence of alloying reactions, compared to those in the contact without a Ni first layer. This suggests an ideal interface structure for a low resistance AuNiGe ohmic contact after alloying to be a uniform two layer structure: a high density of the NiAs(Ge) grains contacting the GaAs substrate, and a homogeneous β‐AuGa phase close to the top surface. However, due to the existence of β‐AuGa phases with a low melting point of around 375 °C, the thermal stability of the contact at 400 °C is of serious concern. Segregation of the NiAs(Ge) grains was observed after annealing at 400 °C for 10 h, which reduced the contact areas between the NiAs(Ge) grains and GaAs. During subsequent annealing at this temperature for up to 90 h, liquidlike flow of the β‐AuGa phase was observed which deteriorated the interface uniformity, causing an increase in contact resistance. A typical contact edge slide distance after contact alloying at 440 °C for 2 min was measured to be 0.2 μm and the longest distance among specimens examined was 0.47 μm. This edge deterioration could limit the use of the AuNiGe contact in GaAs submicron devices.

Modeling and measurement of contact resistances

Abstract: This paper presents a generalized model of ohmic contacts and a unified approach for the accurate extraction of specific contact resistivity (ρ c ) for ohmic contacts from measured contact resistance using the cross bridge Kelvin resistor, the contact end resistor, and the tranmsission line tap resistor test structures. A general three-dimensional (3-D) model of the contacts has been developed from the first principles and has been reduced to 2-D, 1-D, and 0-D (one lump) models with the necessary approximations. It is shown that the conventional I-D models overestimate the value of ρ c because of the parasitic resistance due to 2-D current flow around the periphery of the contact window. Using 2-D simulations, we have accurately modeled the current crowding effects and have extracted accurate values of ρ c independent of contact size and the test structure type. A theory of scaling of contacts has been developed and is applied to commonly used structures. A universal set of curves has been derived for each particular contact resistance test structure and, given the geometry of the structure, these allow accurate determination of ρ c , Without the actual use of the 2-D simulator. Experimental and theoretical accuracy of the three test structures has been compared. Accurate values of ρ c for various contact materials to n+and ρ+Si have been determined. The data confirm that in the past researchers have overestimated ρ c , and that ρ c will not limit device performance even with submicrometer design rules.

The impact of intrinsic series resistance on MOSFET scaling

Abstract: The intrinsic parasitic series resistance associated with the practical structure of a MOSFET is examined. The components considered include contact resistance, diffusion sheet resistance, spreading (injection) resistance, and accumulation layer resistance. The impact of the total resistance on MOSFET scaling is assessed, down to a channel length of 0.15 µm. The results show that, contrary to what has been claimed before, the transconductance and current of a MOSFET continue to increase as the channel length is miniaturized, although the degradation percentage-wise compared to an ideal device without series resistance continues to increase. Based on the degraded I-V characteristics and their effects on an inverter, it is shown here that for NMOS or PMOS digital circuits, the maximum degradation in speed due to series resistance is 20-35 percent compared to ideal scaling for the shortest channel considered. For CMOS circuits, the maximum degradation is reduced to 7-15 percent. In absolute terms, a loss of speed in either case due to miniaturization of channel length is not expected even down to 0.15 µm.

A self-aligned CoSi 2 interconnection and contact technology for VLSI applications

Abstract: Cobalt silicide is investigated in view of possible application in a self-aligned technology. Extremely smooth, highly conductive CoSi 2 films are obtained using rapid thermal processing for silicide formation starting from deposited cobalt layers (on Si). The phase formation is studied by XRD and RBS. No lateral silicide formation is observed at contact edges. The influence of Si consumption and dopant behavior on diode performance is studied. Shallow arsenic (0.15 µm deep) and boron (0.3 µm deep) junctions are successfully silicided. Very low contact resistances are obtained between the silicide and n+ and p+ regions. MOS transistors were fabricated with CoSi 2 on the source, drain, and gate. An increase in current driving capability is noticed while no degradation of other electrical parameters due to the silicide processing steps is observed. At some critical points, comparison is made with the TiSi 2 process.

Fretting corrosion of Tin-plated copper alloy

Abstract: The rise in contact resistance of a tin-plated copper alloy under cyclical minute motion has been studied for both dry circuit and with electrical loads. In the range of circuit voltage and current investigated, the electrical conduction through slightly corroded contacts is shown not to be affected by the electrical load. For moderately corroded contacts, the resistance characteristic shows a sustained plateau near the melting voltage of Sn; and for severely corroded contacts, plateau occurs in the resistance range corresponding to the voltage range of the melting, sublimation, and decomposition of the oxides and the vaporization of tin. Based on our observation, a consistent picture of fretting corrosion and electrical conduction through such contacts is presented.

IMPROVED LOW CONTACT RESISTANCE IN HIGH-T//c Y-Ba-Cu-O CERAMIC SUPERCONDUCTORS

Abstract: One of the important problems for electrical applications of high-temperature superconductors is the contact resistance between the superconductor and a normal metallic wire. In this paper, the authors report a simple method of contact preparation for high-T//c copper-oxide materials (Y-Ba-Cu-O). Based on high-temperature metallization, it reduces the contact resistance from typically 1 OMEGA mm** minus **2 down to APP 1STH 10 mu OMEGA mm** minus **2 (77 K), and makes it possible to measure the critical current of a bulk sample, with current densities in the contact area in excess of 2000 A cm** minus **2.

Source—Drain contact resistance in CMOS with self-aligned TiSi 2

Abstract: The contact resistance between TiSi 2 and n+-p+source-drain in CMOS is studied for a variety of junction profiles and silicide thicknesses. It is shown that the measured contact resistance is consistent with the transmission-line model for electrically long contacts. The contact contribution to the total device series resistance can be significant if excessive silicon is consumed during silicide formation. Contact resistivities of 3 × 10-7and 1 × 10-6Ω . cm2can be obtained for 0.15-0.20-µm-deep arsenic and boron junctions, respectively, if the interface doping concentration is kept at 1 × 1020/cm3. Furthermore, low-temperature measurements show that the contact resistivity is nearly constant from 300 to 77 K, as would be expected from a tunneling-dominated current transport at the TiSi 2 -n+and TiSi 2 -P+interfaces.

Thermally stable, low‐resistance NiInW ohmic contacts to n‐type GaAs

Abstract: A new thermally stable, low‐resistance NiInW contact metal to n‐type GaAs has been developed by depositing a thin In layer with Ni and W layers and annealing at elevated temperatures for a short time. Low resistances of ∼0.3 Ω mm were obtained at annealing temperatures in the range of 800 to 1000 °C. The contact resistances were stable during subsequent annealings at 400 °C for 100 h and 500 °C for 10 h. The thermal stability of the contact resistance and the surface morphology of this contact are superior to those of the conventionally used AuNiGe contacts and this new contact is suitable for various device applications. Further reduction of the contact resistance can be achieved simply by reducing the sheet resistance of the contact metals.

Direct silicidation of Co on Si by rapid thermal annealing

Abstract: Rapid thermal annealing is used to form cobalt silicide directly on unimplanted as well as B-, As-, and P-implanted wafers. The films are characterized by sheet resistance, X-ray diffraction, SEM, TEM, SIMS, and contact resistance measurements. The direct silicidation of Co on Si by rapid thermal annealing yields smooth low-resistivity films with minimal dopant redistribution.

Thermally stable ohmic contacts to n‐type GaAs. II. MoGeInW contact metal

Abstract: It was previously found that a small amount of In impurity was able to convert MoGeW contacts from Schottky to ohmic behavior yielding thermally stable, low‐resistance ohmic contacts n‐type GaAs. In the present experiment transport measurements and materials studies were carried out for MoGeInW contacts in which a thin layer of In was directly added to the MoGeW contacts during deposition. The transition from Schottky to ohmic behavior was observed by adding an In layer as thin as ∼1 nm to the MoGeW. Contact resistances were found to be very sensitive to the deposition sequence, the annealing method, the annealing temperature, and the In layer thickness. Low resistances of ∼0.5 Ω mm were obtained in the MoGeInW contacts with 2‐nm‐thick In layers, annealed by the heat‐pulse method at temperatures in the range of 880–960 °C for 2 s. Contact resistances were stable during subsequent annealing at 400 °C for 100 h. Evidence of formation of the parallel diode areas with various barrier heights was obtained for ...

A heater made from graphite composite material for potential deicing application

Abstract: A surface heater was developed using a graphite fiber-epoxy composite as the heating element. This heater can be thin, highly electrically and thermally conductive, and can conform to an irregular surface. Therefore it may be used in an aircraft's thermal deicing system to quickly and uniformly heat the aircraft surface. One-ply of unidirectional graphite fiber-epoxy composite was laminated between two plies of fiber glass-epoxy composite, with nickel foil contacting the end portions of the composite and partly exposed beyond the composites for electrical contact. The model heater used brominated P-100 fibers from Amoco. The fiber's electrical resistivity, thermal conductivity and density were 50 micro ohms per centimeter, 270 W/m-K and 2.30 gm/cubic cm, respectively. The electricity was found to penetrate through the composite in the transverse direction to make an acceptably low foil-composite contact resistance. When conducting current, the heater temperature increase reached 50 percent of the steady state value within 20 sec. There was no overheating at the ends of the heater provided there was no water corrosion. If the foil-composite bonding failed during storage, liquid water exposure was found to oxidize the foil. Such bonding failure may be avoided if perforated nickel foil is used, so that the composite plies can bond to each other through the perforated holes and therefore lock the foil in place.

HEMT with nonalloyed ohmic contacts using n + -InGaAs cap layer

Abstract: We have investigated nonalloyed ohmic contacts on HEMT's using a highly conductive n+-InGaAs layer. The minimum specific contact resistance obtained was 4.8 × 10-7Ω.cm2, and the IV characteristics were equal to or better than those of conventional HEMT's with alloyed ohmic contacts. The maximum transconductances of a nonalloyed ohmic HEMT were 240 mS/mm at 300K and 340 mS/mm at 88K for a gate length of 1.1 µm. We conclude that it is not necessary for HEMT's with two-dimensional electron gas (2DEG) channels to have alloyed ohmic contacts, because the tunneling conduction is significant at the n-GaAs/n-AlGaAs/undoped GaAs double heterojunction.

The effect of lateral current spreading on the specific contact resistivity in D-resistor Kelvin devices

Abstract: The effects of lateral current spreading on the determination of ohmic contact resistivity when Using Kelvin devices with a D-resistor layout are studied by numerical simulation and experimental measurements. Simulations show that the extracted contact resistivity can be higher or lower than the actual resistivity. The extracted contact resistivity is found to be a strong function of the geometrical layout, the semiconductor sheet resistance, and the actual contact resistivity. Futhermore, it is shown that the actual contact resistivity cannot be determined below some minimum value and the effect of misalignment during processing is shown to produce significant errors. Good agreement with the experiment is found for As-implanted ohmic contacts to Si. Guidelines for the design, processing, and evaluation of D-resistor Kelvin devices are presented.

Rapid thermal alloyed ohmic contact on InP

Abstract: The results of a study of the electrical and metallurgical properties of thin metallic layers deposited on InP for use as an ohmic contact are presented. A rapid thermal annealing system was used to alloy AuGe/Ni/Au contacts ton-type ion implanted InP. Rutherford backscattering and contact resistivity measurement were used to evaluate the structural and electrical characteristics of these rapid thermal alloyed thin films. Varying degrees of mixing between the metals and the semiconductor were found depending on the temperature and temperature-time cycle. These results were compared to furnace and graphite strip-heater alloying techniques. A correlation between the interface structure and the contact resistance was found. Temperatures between 430 and 450° C and alloying time of 2 sec have produced the best electrical results, with specific contact resistance as low as 2*10−7 Ω cm2 on semi-insulating InP which was Siimplanted with a peak concentration about 2*1018 cm−3. The optimum alloy temperature is marked by the onset of substantial wrinkling of the contact surface, whereas essentially smooth surfaces are obtained at temperatures below optimum. The depth of the alloyed ohmic contact is controlled by the time of heating and could be less than 1000A.

High performance half-micron PMOSFETs with 0.1um shallow P + N junction utilizing selective silicon growth and rapid thermal annealing

Abstract: High performance half-micron PMOSFETs with extremely shallow junction and low parasitic resistance have been realized utilizing selective silicon growth(SSG) with rapid thermal anneal(RTA) processing. In the technology, SSG greatly contributes to reduction of effective junction depth for MOSFETs because of raised source/drain(S/D) structures, and RTA can effectively reduce the junction depth, S/D resistance, and contact resistance due to its excellent activation characteristics of implanted ions and anneal-out of fluorine induced defects. By combining SSG with RTA, shallow P+N junction of 0.1µm depth, sheet resistance of 56ohm/square, and contact resistance of 30ohms for 0.8µm2contact were achieved simultaneously. Moreover, this device structure can provide relaxed alignment tolerances as well as more reliable contact characteristics by avoiding aluminum spiking. The feasibility of the fabrication process and device structure has been demonstrated.

Current crowding and misalignment effects as sources of error in contact resistivity measurements—Part I: Computer simulation of conventional CER and CKR structures

Abstract: In this paper we have investigated current crowding and misalignment effects as sources of error in the extraction of the contact resistivity from contact resistance data. Computer simulations have been carried out to analyze both conventional CER and CKR structures. The extent of the errors related to such parasitic effects is discussed, with particular emphasis on the effect of current crowding in misaligned contacts, in the case where the contact geometry is not correctly taken into account.

A highly reliable selective CVD-W utilizing SiH4 reduction for VLSI contacts

Abstract: Selective CVD-W process by using silane (SiH4) reduction of WF6 has been developed for VLSI contacts The reaction occurs very fast resulting in a deposition rate of as high as 06 µm/min, and completely suppresses undesirable phenomena such as encroachment and wormholes An X-ray diffraction analysis shows that a small W5Si3 peak can be observed although W peaks are dominant The junction leakage current for the new selective CVD-W process is almost the same as that for conventional AlSi one Contact resistance of submicron holes is more stable and lower for this process than for the conventional one This new process has been successfully applied to CMOS 1Mbit DRAM

Comparison of the Inherent Arc Erosion Behaviors of Silver-Cadmium Oxide and Silver-Tin Oxide Contact Materials

Abstract: Powder metallurgically produced silver-cadmium oxide and silver-tin oxide materials with equal volume percentages of oxide were electrically tested to evaluate and compare the effects of the different oxides on the arc erosion behaviors. The silver-tin oxide material had less steady-state erosion, better weld resistance, and higher contact resitance compared to silver-cadmium oxide. The eroded surface structures were examined and used to explain these quantitative results. The arc-affected erosion surfaces of the silver-tin oxide material consisted of silver, tin oxide, and porosity distributed across the contact surface, yielding Iow weld strengths but high contact resistance. The silver-cadmium oxide eroded surfaces had large elevated oxide-depleted areas which yielded Iow contact resistance but higher weld strengths. Theories of how these 'eroded surface structures developed under the given conditions are presented for the silver-cadmium oxide and the silver-tin oxide materials.

An improved AuGeNi ohmic contact to n-type GaAs

Abstract: The relation of contact resistance to heat treatment and microstructure was examined for the three following ohmic contact metallizations on n -GaAs: 200 A Ge/200 A Ni/2000 A Au, 200 A AuGe/200 A Ni/2000 A Au and 1000 A AuGe/200 A Ni. After an initial anneal at 440°C, the Ge/Ni/Au metallization had the lowest contact resistance and the highest proportion of the NiGeAs phase at the GaAs/contact interface. It was also the most stable with subsequent ageing at 330°C, this stability being attributed to the NiGeAs phase acting as a diffusion barrier at the GaAs/contact interface.

HPSAC—A silicided amorphous-silicon contact and interconnect technology for VLSI

Abstract: A high-performance silicided amorphous-silicon contact and interconnect technology (HPSAC) for VLSI is presented. In this novel scheme, a patterned silicide layer is used to form self-aligned contacts to the source/drain regions, as well as to interconnect devices. The fabrication procedures and some key processing techniques are described, Experimental results on n-and p-channel MOSFET's fabricated with HPSAC technology are presented. The performance improvement due to reduction of parasitic capacitance and resistance is discussed.

A highly reliable interconnection for a BF + 2 -implanted junction utilizing a TiN/Ti barrier metal system

Abstract: A submicrometer-rule interconnection structure of the Al-Si layer to the BF 2 +-implanted Si region is described. The contact resistance of Al-Si to BF 2 +-implanted Si increases more than those to B+- or As+-implanted Si, as contact hole size is scaled down to around 1 µ2. Through SEM and TEM analyses, it is found that solid phase epitaxial growth of Si takes place on the contact interfaces, where crystalline defects induced by BF 2 +implantation act as seeds. Thus, the effective metal contact area to Si is reduced very much. In order to realize a stable metallization system, a TiN/Ti barrier metal structure is introduced. The TiN/Ti structure is optimized in terms of contact resistance and contact barriers, and its feasibility for submicrometer-rule CMOS VLSI's is clarified.

New Models and Methodology for Predicting Thermal Contact Resistance in Compound Cylinders and Finned Tubes

Abstract: New thermal conductance correlations based on improved metal, gap. and joint contact models are presented for determining the thermal inlerfacial resistance in compound cylinders. The new theory utilizes models involving measured surface parameters, material hardness, thermophysical properties, and ileratively evaluated contact stresses. The predictions of previous and proposed models are compared to recently published experimental investigations on compound cylinders. Accuracy to within 5% of experimental data is obtained by means of the proposed models. It was found that the alternative models grossly overestimated the thermal contact resistance in compound cylinders, with error ranges from 25 to 100% (Ross and Stoute, Shlykov and Ganin) and 100 to 200% (Veziroglu) of the experimental results. The experimental verifications thereby support the new models in the analysis of compound cylinders, with direct applications in analyzing the performance of finned-tube heal exchangers.

Bipolar transistor with self-aligned lateral profile

Abstract: This paper presents a new self-alignment concept for scaled-down bipolar transistors: the self-aligned lateral profile. Using this concept to form the impurity profile and combining it with a wraparound base contact to reduce the emitter-base contact spacing and an n+-poly-refractory metal emitter stack to reduce the emitter resistance, a high-performance and potentially high-yield device structure can be obtained. The device structure can be adapted to a CMOS or merged bipolar-CMOS process and can also be easily optimized for analog applications.

Semiconductor device and manufacture thereof

Abstract: PURPOSE:To suppress the increase in the contact resistance value by a method wherein the side wall and the bottom of a contact hole are covered with a conductive layer made of refractory metal or its silicide and the upper part of the hole is made flat by depositing polycrystalline silicon into the concave part of the surface of the contact hole CONSTITUTION:An n-type diffused region 2 is formed on a P-type single-crystal silicon substrate 1, and an interlayer silicon oxide film 3 having a contact hole 4 on its main surface is formed A tungsten silicide film 5 is formed so that the surface of the interlayer silicon oxide film 3 as well as the side wall and the bottom of the contact hole 4 can be covered Polycrystalline silicon 7 is deposited in the concave part on the tungsten silicide film 5 of the contact hole 4 so that the upper part can be made flat Then an aluminium wire 8 is formed on the flat surface Through this constitution, there is no concern for the breaking of the aluminium wire 8, and the electrical connection of the aluminium wire 8 with the n-type diffused region 2 is achieved via the tungsten silicide film 5 of low resistance so that the resistance can be reduced

Thermally stable ohmic contacts to n‐type GaAs. I. MoGeW contact metal

Abstract: Thermally stable, low‐resistance ohmic contacts on n‐type GaAs are required to fabricate high‐speed GaAs integrated circuits. MoGeW contacts prepared by annealing at high temperature around 800 °C in an InAs overpressure are attractive, because the contact is expected to be thermally stable during subsequent annealing at 400 °C, which is required by several process steps following ohmic contact formation. In the present experiment, the contact resistance measurements and microstructural analysis of MoGeW contacts were carried out to establish a fabrication process which forms ohmic contacts with low contact resistance. The contact metals were prepared by sequentiallydepositing Ge, Mo, Ge, and W, with various Mo/Ge layer thickness ratios, onto (100)‐oriented GaAs wafers. The conducting channels were formed by doping GaAs with about 1×1018 cm−3 Si. Contact resistances were determined by the transmission line method, and microstructural analysis was carried out by x‐ray diffraction, Auger electron spectrosco...