Showing papers on "Current divider published in 2003"

Modified Wilkinson power divider for nth harmonic suppression

Abstract: This paper presents a structure of the Wilkinson power divider that can suppress the nth harmonic output. The power divider consists of two /spl lambda//4n open stubs, which are located at the center of /spl lambda//4 branches and a parallel connection of a resistor and an inductor, which shunts the output ports. Experimental results show that this power divider suppresses the third harmonic component to less than -40 dB, while maintaining the characteristics of a conventional Wilkinson power divider; featuring an equal power split, a simultaneous impedance matching at all ports and a good isolation between output ports. These results agree quite well with the simulation results.

Design and realisation of dual-band 3 dB power divider based on two-section transmission-line topology

Abstract: A new dual-band 3 dB three-port power divider with arbitrary impedance terminations is proposed. The structure is composed of a two-section transmission-line transformer and an isolation resistor. Each transmission line's electrical length is /spl pi//3 at the fundamental frequency. Based on an ideal transmission line model, new design equations and graphs are given. The technique is validated by the experimental results on a 3 dB 900/1800 MHz power divider with Z/sub S/=100 /spl Omega/ and Z/sub L/=50 /spl Omega/. Good performances of the proposed power combiner/divider at both frequencies are obtained.

Pico-A/V range CMOS transconductors using series-parallel current division

Abstract: A simple design procedure for very small transconductors with extended linear range, using series-parallel division of current, is presented. It is based on a previously reported one-equation all-region transistor model. Using this technique, a 33 pico-A/V transconductor equivalent to a 30 GΩ resistor is demonstrated.

Ultracapacitor balancing circuit

Abstract: The present invention provides an energy storage system comprising at least one voltage source, and a string of series connected cells, wherein each of the cells is connected to a circuit, wherein the circuit comprises at least one voltage reference, at least one voltage divider, which sets a trip point, and at least one operational amplifier, wherein at least one operational amplifier receives a first input from voltage reference and a second input from voltage divider and shunts an output through a power dissipative device when voltage of a cell exceeds said trip point.

Digital frequency tuning technique based on current division for integrated active RC filters

Abstract: A novel digital frequency tuning technique is presented for integrated active RC filters. Instead of varying the values of the capacitors or resistors as in traditional approaches, the proposed technique achieves frequency tuning by dividing the currents that flow from resistors to virtual grounds. Current division is performed through a digitally programmable current division network added at each virtual ground. The technique features compact size, wide tuning range and high linearity. Transistor level simulation results are presented to demonstrate the technique.

Phase locked loop circuit using fractional frequency divider

Abstract: There is provided a phase locked loop circuit capable of obtaining an output frequency having no fraction even in case a reference signal has a rounded frequency (e.g., 10 MHz). The phase locked loop circuit uses a fractional frequency divider, comprises: a first PLL stage for controlling the output frequency of a first voltage-controlled oscillator with a deviation, which is obtained by dividing the frequency of the output of the first voltage-controlled oscillator by a first fractional frequency divider and by comparing the frequency-divided output with a reference frequency, through a low-pass filter; and a second fractional frequency divider for dividing the frequency of the output of the first PLL stage and for inputting the frequency-divided output as a reference frequency signal of a second PLL stage. The output signal of a second voltage-controlled oscillator of the second PLL stage is extracted.

18 GHz low-power CMOS static frequency divider

Abstract: A pseudo-differential latch circuit is investigated. By removing the current source from the conventional source-coupled field-effect-transistor logic (SCFL) structure, the speed of the circuit can be improved. The pseudo-differential D-type flip-flop-based 2:1 static frequency divider, which can operate up to 18 GHz and consumes less than 4 mA from a 1.8 V supply, has been realised in 0.18 µm standard digital CMOS technology.

Control circuit for supplying a current to display devices

Abstract: A control circuit includes a plurality of drive current output circuits, a control voltage generating circuit, a first current output circuit, a second current output circuit, a voltage divider and a compensation voltage generating circuit. The voltage divider has one end connected to the control voltage generating circuit and a plurality of nodes each of which connected to the respective drive current output. The drive current output circuit outputs the control voltage to the drive circuits based on a power supply voltage and the control voltage. The compensation voltage generating circuit outputs a compensated voltage based on the difference between the current outputted from the first current output circuit and the current outputted from the second current output circuit. In order to supply the compensation voltage to the other end of the voltage divider, the values of the respective control voltage are equalized.

Monotonic precise current DAC

Abstract: A monotonic digital-to-analog converter (DAC) for converting a digital input signal into an analog output signal comprises: an input node for receiving the digital input signal having at least M+L bits, an output node for delivering the analog output signal corresponding to the received digital input signal, a coarse conversion block comprising current sources and first switching means for converting M more significant bits of the digital input signal into a coarse block output current, a fine conversion block comprising a current divider and second switching means for converting L less significant bits of the digital input signal into a corresponding current value, the fine conversion block having means for receiving current from a first unselected current source of the coarse conversion block, and a first cascode means for active cascoding the coarse block output current, a second cascode means, for active cascoding the current from the first unselected current source. A method for converting a digital input signal into an analog output signal is also provided.

1.5 V four-quadrant CMOS current multiplier/divider

Abstract: A low voltage CMOS four-quadrant current multiplier/divider circuit is presented. It is based on a compact V-I converter cell able to operate at very low supply voltages. Measurement results for an experimental prototype in a 0.8 /spl mu/m CMOS technology show good linearity for a /spl plusmn/15 /spl mu/A input current range and a 1.5 V supply voltage.

Current mirror compensation circuit and method

Abstract: A current compensation circuit for use with a current mirror is disclosed. The current mirror circuit has a current path defined by a first current mirror stage driving a second current mirror stage, the second current mirror stage is coupled to a supply voltage source. The current compensation circuit comprises an impedance divider coupled to the supply voltage and an output node. The impedance divider operates to generate a compensation signal at the node representative of voltage changes in the supply voltage source. The compensation circuit further includes a gain stage having an input coupled to the output node and a current output connected to the current path. The gain stage operates to generate a compensation current for application to the current path in response to the compensation signal.

Integrated N-way Wilkinson power divider/combiner

Abstract: An integrated N-way Wilkinson power divider is described. In one embodiment, the N-way Wilkinson power divider uses a conductor layer with a cross-over (or cross-under) resistor insulated from the conducting layer by an insulating bridge. In one embodiment, the width of the transmission line underneath a cross-over resistor is adjusted to improve performance In one embodiment, a three-way Wilkinson power divider is formed using microstrip transmission lines on a single-layer substrate that supports the microstrip transmission lines, dielectric insulators, and resistors.

Low noise divider module for use in a phase locked loop and other applications

Abstract: A low noise divider module includes a divider chain and a retiming module. The divider chain includes a plurality of cascaded dividers and a plurality of load logic gates. The plurality of cascaded dividers are operably coupled to divide an input oscillation by a divider value, which is programmable, to produce a divided output oscillation based on the load signals provided by the logic gates. The retiming module includes a duty cycle module and a jitter reduction module. The duty cycle module is coupled to produce a duty cycle controlled output oscillation based on a representation of the divided output oscillation produced by the divider chain in accordance with a duty cycle setting signal. The jitter reduction module is operably coupled to produce a low jitter output oscillation from the duty cycle controlled output oscillation based on the input oscillation and the duty cycle setting signal.

Voltage divider circuit

Abstract: PROBLEM TO BE SOLVED: To provide a voltage divider circuit that is configured to be capable of outputting a highly accurately divided DC voltage with a comparatively simple structure. SOLUTION: Two semiconductor switches Sd1, Sd2 connected in series and having diodes D1, D2 connected inversely parallel, two semiconductor switches Sd3, Sd4 connected in series and having diodes D3, D4 connected inversely parallel, and voltage divider capacitors Cd1, Cd2 connected so as to divide an output voltage by a desired voltage ratio are connected between upper and lower terminals of a DC voltage source VO. Furthermore, the middle point 'a' of the semiconductor switches Sd1, Sd2 is connected to the middle point 'c' of the voltage divider capacitors Cd1, Cd2 via a voltage limiting element Ld1, and the middle point 'b' of the semiconductor switches Sd3, Sd4 to the middle point 'c' of the voltage divider capacitors Cd1, Cd2 via another voltage limiting element Ld2. The voltage divider circuit is formed by winding inductors, which are the voltage limiting elements Ld1, Ld2, on a common iron core 23. COPYRIGHT: (C)2005,JPO&NCIPI

Design of a multiple-way power divider for center-feed single-layer waveguide arrays

Abstract: Center feed in single-layer slotted waveguide arrays was proposed to increase the frequency bandwidth depending on the long line effect and to obtain a stable main beam unchanged for frequencies. The feed waveguide in this structure is placed at the middle of the radiating waveguides and is composed of a series of unit dividers called a cross-junction. This paper deals with the practical design of a multiple-way power divider for the center feed. A 16-way power divider is designed at 25.3 GHz as an example.

High voltage regulation circuit to minimize voltage overshoot

Abstract: A resistive divider for a voltage multiplier circuit minimizes output voltage overshoot by capacitively coupling the tap point of the resistive divider to the output terminal of the voltage multiplier circuit via the parasitic capacitance of the resistive divider. For a resistive divider that includes a resistive structure formed over a dielectric layer formed on a doped well, this capacitive coupling can be performed by connecting the well to the output terminal of the voltage multiplier circuit. This capacitive coupling improves the response time of the resistive divider, so that a scaled test voltage read from the tap point varies more rapidly than the elevated output voltage of the voltage multiplier circuit. Therefore, the scaled test voltage provides charging control that increases the elevated output voltage in gradual increments that prevent the elevated output voltage from exceeding a target output voltage.

Reference voltage generating circuit capable of controlling temperature dependency of reference voltage

Abstract: A constant current which is output from a constant current circuit having a positive temperature characteristic and a constant current which is output from a constant current circuit having a negative temperature characteristic are both input to a current synthesizing circuit. The current synthesizing circuit synthesizes the constant currents at a ratio which allows a temperature characteristic to be within a range between the positive temperature characteristic and the negative temperature characteristic and accordingly outputs a constant current having an arbitrary temperature dependency within a specific range. The constant current output from the current synthesizing circuit is input to a current-voltage converting circuit to be converted into a reference voltage.

1V 2GHz CMOS frequency divider

Abstract: A new frequency divider, called differential injection locking, is proposed. The proposed divider has no transistor stacking to suppress the performance degradation due to supply voltage reduction. It is shown that the proposed frequency divider achieves 2 GHz with 1 V supply voltage and 540 /spl mu/W power consumption.

DC voltage divider calibration system at NMIJ

Abstract: A system to self-calibrate a DC voltage divider with increment taps up to 1 kV has been developed. During self-calibration, the divider is grounded and is powered at the same level as it is when in normal use. A reference divider self-calibrated by this method is used as a standard to calibrate other dividers at NMIJ. Typical relative uncertainty is 3/spl times/10/sup -7/ for 1000 V/10 V and 2/spl times/10/sup -7/ for 100 V/10 V (k=2, confidence level of 95%).

Video cassette recorder and RCC type switching power supply

Abstract: An error detection circuit includes: a Zener diode having a cathode connected through a resistor to a second DC output with a higher voltage than that of a first DC output; a voltage divider circuit; and a PNP transistor having an emitter connected to the first DC output, and a base supplied with an output voltage of the voltage divider circuit. A Zener voltage of the Zener diode and a voltage dividing ratio of the voltage divider circuit are set so that the output voltage of the voltage divider circuit is equal to a value obtained by subtracting the base-emitter voltage of the PNP transistor Q 1 from the voltage of the first DC output, and that temperature characteristic of the output voltage of the voltage divider circuit is set at a value canceling temperature characteristic of the PNP transistor.

Regulator circuit for independent adjustment of pumps in multiple modes of operation

Abstract: A regulator circuit with at least two independently selectable and adjustable adjustment circuits. Each adjustment circuit may be connected across a standard voltage divider circuit used to create a reference voltage for operating a voltage pump. Between each adjustment circuit and the voltage divider circuit is an associated connection circuit that is controlled by an associated control signal. When activated by its respective control signal, the connection circuit connects its associated adjustment circuit to the voltage divider circuit so that the reference voltage is generated by the voltage divider as adjusted by the connected adjustment circuit. The amount of adjustment each adjustment circuit can introduce is independently selectable, the regulator circuit can adjust the operation of the pump for different modes of operation and can compensate for process variations without the need to re-design, re-mask or re-fabricate the circuitry.

Frequency-independent voltage divider

Abstract: The present invention relates to a frequency-independent voltage divider in which a compensation structure (10) for compensating a distributed parasitic capacitance of a resistor arrangement (20) is arranged between the resistor arrangement (20) and a substrate (50). Thereby, the compensation structure (10) shields the resistor arrangement (20) partly from the substrate (50), and thus shields the parasitic capacitance. This allows for an improved compensation.

Trim circuit and method for tuning a current level of a reference cell in a flash memory

Abstract: A trim circuit and method for tuning a current level of a reference cell in a flash memory that includes a sense amplifier to compare a cell current from a memory cell whose gate receives a word line signal voltage with a reference current from the reference cell whose gate receives a bias voltage produced by dividing the word line signal voltage by a voltage divider to thereby produce a sense signal. The voltage divider includes at least a programmable flash cell to serve as a variable resistor whose resistance is determined by programming the programmable flash cell by a programming/erasing circuit in reference to the programming of the memory cell.

Current driver circuit

Abstract: A current driver circuit has a current driver and a current compensation circuit. The current driver has a current source transistor connected to a power source potential level, while it is coupled to a pair of transmission lines. The current compensation circuit is coupled to the output side of the current source transistor for the compensation of an output current from the current driver in response to a common mode potential of the pair of transmission lines.

A Family of LowPower Truly Modular Programmable Dividers in Standard 0.35m CMOS Technology

Abstract: A truly modular and power-scalable architecture for low-power programmable frequency dividers is presented. The architecture was used in the realization of a family of low-power fully programmable divider circuits, which consists of a 17-bit UHF divider, an 18-bit L-band divider, and a 12-bit reference divider. Key circuits of the architecture are 2/3 divider cells, which share the same logic and the same circuit implementation. The current consumption of each cell can be determined with a simple power optimization procedure. The implementation of the 2/3 divider cells is presented, the power optimization procedure is described, and the input amplifiers are brieny discussed. The circuits were processed in a standard 0.35 µm bulk CMOS technology, and work with a nominal supply voltage of 2.2 V. The power efficiency of the UHF divider is 0.77 GHz/mW, and of the L-band divider, 0.57 GHz/mW. The measured input sensitivity is

Voltage regulation using current feedback

Abstract: A circuit having a voltage regulated by a reference current. The circuit includes a current feedback loop and a reference current source that is capable of producing a reference current. The current feedback loop includes an output device, a voltage to current converter, and a current feedback element. The voltage to current converter is coupled to the output device. A node of the voltage to current converter is the regulated voltage. The current feedback element is coupled to the voltage to current converter to provide a feedback current from the voltage to current converter to compare with the reference current to produce an error signal that is input to a control terminal of the output device. Thus, the current feedback loop regulates the voltage at the node of the voltage to current converter.

Programmable linear-in-dB or linear bias current source and methods to implement current reduction in a PA driver with built-in current steering VGA

Abstract: Programmable linear-in-dB or linear bias current source with respect to an input voltage is provided. The linear-in-dB or linear bias current may be clipped at a minimum current level, a maximum current level, or a combination thereof. Preferably, the minimum and maximum current levels are determined by the use of one or more constant current sources. The constant current sources limit the amount of voltage applied to the gates of one or more transistors, which in turn control the output current. The use of the circuit may be used to generate linear or reverse-linear current levels with respect to an input voltage. The output of the current generator may be used as an input to a power-amplifier driver, for example.

Non-integer frequency divider circuit

Abstract: A non-integer frequency divider is disclosed. The non-integer frequency divider circuit includes several base stages connected to each other. The non-integer frequency divider circuit also includes a clocking circuit for passing an enable bit from one of the base stages to another such that only one of the base stages is enabled at any give time. The enable bit has a pulse width of one clock cycle. The outputs from the base stages are grouped together by an OR gate to generate a single output that is a fraction of an input clock signal.

Frequency synthesizer for reducing noise

Abstract: A fractional-N frequency synthesizer includes a first divider, a second divider, and a division ratio controller. The first divider receives and divides an oscillation frequency signal. The second divider receives a predetermined feedback frequency signal and divides the feedback frequency signal in response to a selection signal. The division ratio controller receives and divides an output signal of the first divider and an output signal of the second divider and generates a reference frequency signal in which the oscillation frequency signal is divided, a comparison frequency signal that is compared with the reference frequency signal, and the selection signal used to select the division ratio of the second divider.