Showing papers on "Depletion region published in 2004"

Semiconductor device, manufacturing method, and electronic device

Abstract: In a thin film transistor ( 1 ), a gate insulating layer ( 4 ) is formed on a gate electrode ( 3 ) formed on an insulating substrate ( 2 ). Formed on the gate insulating layer ( 4 ) is a semiconductor layer ( 5 ). Formed on the semiconductor layer ( 5 ) are a source electrode ( 6 ) and a drain electrode ( 7 ). A protective layer ( 8 ) covers them, so that the semiconductor layer ( 5 ) is blocked from an atmosphere. The semiconductor layer ( 5 ) (active layer) is made of, e.g., a semiconductor containing polycrystalline ZnO to which, e.g., a group V element is added. The protective layer ( 8 ) thus formed causes decrease of a surface level of the semiconductor layer ( 5 ). This eliminates a depletion layer spreading therewithin. Accordingly, the ZnO becomes an n-type semiconductor indicating an intrinsic resistance, with the result that too many free electrons are generated. However, the added element works on the ZnO as an accepter impurity, so that the free electrons are reduced. This decreases a gate voltage required for removal of the free electrons, so that the threshold voltage of the thin film transistor ( 1 ) becomes on the order of 0 V. This allows practical use of a semiconductor device which has an active layer made of zinc oxide and which includes an protective layer for blocking the active layer from an atmosphere.

Semiconductor device, its manufacturing method, and electronic device

Abstract: A thin film transistor (1) wherein a gate electrode (3) is formed on an insulative substrate (2), a gate insulating layer (4) is formed on the gate electrode (3), a semiconductor layer (5) is formed on the gate insulating layer (4), a source electrode (6) and a drain electrode (7) are formed on the semiconductor layer (5), and a protective layer (8) covering them are formed. The semiconductor layer (5) is isolated from the atmosphere. The semiconductor layer (5) (active layer) is formed of a ZnO polycrystalline semiconductor doped with, for example, a group V element. Since the surface state of the ZnO semiconductor is reduced thanks to the protective layer (8) and inward expansion of the depletion layer is prevented, the ZnO semiconductor is of an n-type showing its intrinsic resistance value and contains excessive free electrons. The added element acts as acceptor impurities in the ZnO semiconductor, decreasing the excessive electrons. Thus the gate voltage to eliminate the excessive free electrons lowers, thereby making the threshold voltage around 0 V. A semiconductor device using a zinc oxide for an active layer and having a protective layer for isolating the active layer from the atmosphere can be actually used.

Glass-based soi structures

Abstract: Semiconductor-on-insulator (SOI) structures, including large area SOI structures, are provided which have one or more regions composed of a layer (15) of a substantially single-crystal semiconductor (e.g., doped silicon) attached to a support substrate (20) composed of an oxide glass or an oxide glass-ceramic. The oxide glass or oxide glass-ceramic is preferably transparent and preferably has a strain point of less than 1000°C, a resistivity at 250°C that is less than or equal to 1016 -cm, and contains positive ions (e.g., alkali or alkaline-earth ions) which can move within the glass or glass-ceramic in response to an electric field at elevated temperatures (e.g., 300 - 1000°C). The bond strength between the semiconductor layer (15) and the support substrate (20) is preferably at least 8 joules/meter2. The semiconductor layer (15) can include a hybrid region (16) in which the semiconductor material has reacted with oxygen ions originating from the glass or glass-ceramic. The support substrate (20) preferably includes a depletion region (23) which has a reduced concentration of the mobile positive ions.

Electrical properties of metal-ferroelectric-insulator-semiconductor structures based on ferroelectric polyvinylidene fluoride copolymer film gate for nonvolatile random access memory application

Abstract: Metal-ferroelectric–insulator-semiconductor device structures with ferroelectric vinylidene fluoride-trifluoroethylene copolymer and SiO2 buffer layer integrated gate stack over n-Si are formed, and their potential for fabricating polymeric nonvolatile random access memory devices is demonstrated. Capacitance-voltage (C–V) studies show that switchable polarization in poled polyvinylidene fluoride PVDF copolymer film changes the Si-surface potential and causes modulation of the Si-surface conductance. The (C–V) hysteresis and bidirectional flatband voltage shift at −10 to +6V, depending on the polarization field direction and remnant polarization at the ferroelectric PVDF copolymer gate, presents a memory window. The space charge at n-Si and switchable polarization both reduce the field across the ferroelectric PVDF. The observed asymmetry of the negative flatband-voltage shifts in the negatively poled ferroelectric polymer state is the result of the depletion layer formation, which reduces the field acros...

Water at hydrophobic substrates: curvature, pressure, and temperature effects.

Abstract: We studied the water density profile close to spherical and planar hydrophobic objects using molecular dynamics (MD) simulations. For normal pressure and room temperature, the depletion layer thickness of a planar substrate is approximately 2.5 Angstroms. Even for quite large spherical solutes with a radius of R = 18 Angstroms, the depletion layer thickness is reduced by 30%, which shows that substrate curvature and roughness is an experimentally important factor. Rising temperature leads to a substantial increase of the depletion layer thickness. The compressibility of the depletion layer is found to be surprisingly small and only approximately 5 times higher than that of bulk water. A high electrostatic surface potential of 0.5 V is found, which presumably plays an important role in the presence of charged solutes, since it can promote adsorption into the interfacial layer.

Theory of spin injection into conjugated organic semiconductors

Abstract: We present a theoretical model to describe electrical spin injection from a ferromagnetic contact into a conjugated organic semiconductor. In thermal equilibrium the magnetic contact is spin polarized, whereas the organic semiconductor is unpolarized. The organic semiconductor must be driven far out of local thermal equilibrium by an electric current to achieve significant spin current injection. However, if the injecting contact has metallic conductivity, its electron distribution cannot be driven far from thermal equilibrium by practical current densities. Thus, quasi-equilibration between the conjugated organic semiconductor and the metallic contact must be suppressed to achieve effective spin injection. This requires a spin-dependent barrier to electrical injection that may be due either to tunneling through the depletion region of a large Schottky barrier or to tunneling through a thin, insulating, interface layer. Schottky barrier formation on conjugated organic semiconductors differs from that on inorganic semiconductors inasmuch as contacts made to organic semiconductors often follow near-ideal Schottky behavior, thus permitting the energy barrier to electrical injection to be varied over a wide range by using metals with different work functions. In addition, insulating tunnel barriers to organic semiconductors based on organic molecules can be conveniently fabricated using self-assembly techniques.

Terahertz emission from p-lnAs due to the instantaneous polarization

Abstract: Terahertz radiation from differently doped n- and p-type InAs crystal surfaces was investigated by time-resolved measurement. Large increase of the emitted terahertz power has been observed for p-InAs samples with the p-doping levels of approximately 1016–1017cm−3. This increase was explained by a large surface depletion layer and an electric-field-induced optical rectification effect in this layer.

Electrical characterization of polymer-based FETs fabricated by spin-coating poly(3-alkylthiophene)s

Abstract: The current-voltage (I-V) characteristics of two different polymer thin-film transistors (TFTs), based on spin-coating of poly(3-hexylthiophene)-P3HT and poly(3-hexadecylthiophene)-P3HDT, are studied. A model is developed to interpret the results and to explain the differences between these two polymers. Various parameters of the semiconducting polymers, including bulk mobility, field-effect mobility, trap density, and unintentional dopant concentration are estimated. The model takes into account the domination of the bulk current over the channel current in the subthreshold regime as well as the effects of the depletion layer as parasitic resistances in series with the channel resistance. Furthermore, the effects of the films thickness on the electrical characteristics of these TFTs are discussed. Compared to the P3HT, the P3HDT-based TFT has a lower subthreshold slope, higher on current ratio, and higher field-effect mobility.

Junction diode comprising varying semiconductor compositions

Abstract: The invention provides for a junction diode including a heavily doped first region having a first conductivity type, a second lightly doped or intrinsic region having a second conductivity type, and a third heavily doped region having a second conductivity type. The junction diode comprises more than one semiconductor or semiconductor alloy. In preferred embodiments, the lightly doped or intrinsic region has a higher proportion of germanium than on or the other or both of the heavily doped regions. In preferred embodiments, the junction diode is vertically oriented, and the top region has a higher proportion of silicon than the other regions.

Efficacy of charge sharing in reshaping the surface electric field in high-voltage lateral RESURF devices

Abstract: A simple one-dimensional (1-D) analytical solution method for analyzing and determining the breakdown properties of reduced surface field (RESURF) lateral devices is presented. The solution demonstrates quantitatively and qualitatively the reshaping and reduction of the electric field and its dependence on the device/process key parameters. The solution is based on a simple and physical charge-sharing approach that takes into account the modulation of the lateral depletion layer spreading caused by the vertical depletion extension, and therefore transforms the inherent two-dimensional effects into a simple 1-D equivalent. It also provides a reasonable insight on the breakdown voltage sensitivity of lateral RESURF devices to key device/process parameters that other researchers failed to provide. Using the technique, device designers can set and choose the optimal processing window of the device's critical layers to yield high breakdown voltages. The results obtained using the proposed solution method agree well with the experimental and simulation results.

Doping profiles in PN diode optical modulators

Abstract: High speed optical modulators can be made of a lateral PN diode formed in a silicon optical rib waveguide, disposed on a SOI or other silicon based substrate. A PN junction is formed at the boundary of the P and N doped regions. The depletion region at the PN junction overlaps with the center of a guided optical mode propagating through the waveguide. Electrically modulating a lateral PN diode causes a phase shift in an optical wave propagating through the waveguide. Each of the doped regions can have a stepped or gradient doping profile within it or several doped sections with different doping concentrations. Forming the doped regions of a PN diode modulator with stepped or gradient doping profiles can optimize the trade off between the series resistance of the PN diode and the optical loss in the center of the waveguide due to the presence of dopants.

Surface depletion in doped SrTiO3 thin films

Abstract: Strong effects of surface depletion have been observed in metallic La-doped SrTiO3 thin films grown on SrTiO3 substrates by pulsed-laser deposition. The depletion layer grows with decreasing temperature due to the large temperature-dependent dielectric response of SrTiO3. When the depletion layer becomes comparable to or exceeds the thickness of the doped film, the Hall mobility shows significant enhancements as more of the electron distribution extends into the undoped substrate, in conceptual analogy to modulation doping in compound semiconductor heterostructures.

Photoelectric conversion apparatus and image pick-up system using the photoelectric conversion apparatus

Abstract: A primary object of the present invention is to provide a photoelectric conversion apparatus with less leak current in a floating diffusion region. In order to obtain the above object, a photoelectric conversion apparatus according to the present invention includes a photodiode for converting light into a signal charge, a first semiconductor region having a first conductivity type, a floating diffusion region formed from a second semiconductor region having a second conductivity type for converting the signal charge generated by the photodiode into a signal voltage, the second semiconductor region being formed in the first semiconductor region, and an electrode formed above the first semiconductor region through an insulating film and having an effect of increasing a concentration of majority carriers in the first semiconductor region, in which the electrode is not formed above a depletion region formed from the second semiconductor region.

Negative band gaps in dilute InNxSb1-x alloys.

Abstract: A thin layer of InNSb has been fabricated by low energy nitrogen implantation in the near-surface region of InSb. X-ray photoelectron spectroscopy indicates that nitrogen occupies ∼6% of the anion lattice sites. High-resolution electron-energy-loss spectroscopy of the conduction band electron plasma reveals the absence of a depletion layer for this alloy, thus indicating that the Fermi level is located below the valence band maximum (VBM). The plasma frequency for this alloy combined with the semiconductor statistics indicates that the Fermi level is located above the conduction band minimum (CBM). Consequently, the CBM is located below the VBM, indicating a negative band gap material has been formed. These measurements are consistent with k p calculations for InN 0 . 0 6 Sb 0 . 9 4 that predict a semimetallic band structure.

Low threshold voltage semiconductor device

Abstract: A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor region and the surface of the semiconductor substrate and having a second conductivity type due to second-conductivity-type active impurities contained in the second semiconductor region. The second semiconductor region contains first-conductivity-type active impurities, whose concentration is zero or smaller than a quarter of a concentration of the second-conductivity-type active impurities contained in the second semiconductor region. An insulating film and a conductor are formed on the second semiconductor region. Third and fourth semiconductor regions of the second conductivity type are formed at the semiconductor surface in contact with the side faces of the second semiconductor region. This semiconductor device is capable of suppressing net impurity concentration variations as well as threshold voltage variations to be caused by a short channel effect or manufacturing variations.

Electron scattering study within the depletion region of the GaN(0001) and the GaAs(100) surface

Abstract: The energy distribution curves (EDCs) of photoelectrons emitted from the GaN(0001) negative electron affinity (NEA) surfaces are investigated along with GaAs(100) NEA surfaces. These experiments are performed at room temperature using 3.82eV laser excitation for GaN and 1.96eV laser excitation for GaAs. We find the main contribution to the total emitted current is the electrons that have lost an average energy of 310meV and 140meV, respectively, in the bandbending region (BBR). We propose that the origin of the energy loss as the electrons exit the solid is due to intervalley phonon scattering in the BBR (scattering of Γ electrons into the L–M valleys for GaN and L valley for GaAs). EDC studies on semiconductor NEA surfaces enable us to investigate the semiconductor electron transport property in the high-field region, which is established internally by the bandbending voltage at the surface.

Nanowire varactor diode and methods of making same

Abstract: A nanowire varactor diode and methods of making the same are disclosed. The structure comprises a coaxial capacitor running the length of the semiconductor nanowire. In one embodiment, a semiconductor nanowire of a first conductivity type is deposited on a substrate. An insulator is formed on at least a portion of the nanowire's surface. A region of the nanowire is doped with a second conductivity type material. A first electrical contact is formed on at least part of the insulator and the doped region. A second electrical contact is formed on a non-doped potion of the nanowire. During operation, the conductivity type at the surface of the nanowire inverts and a depletion region is formed upon application of a voltage to the first and second electrical contacts. The varactor diode thereby exhibits variable capacitance as a function of the applied voltage.

Photodiode having voltage tunable spectral response

Abstract: A photodetector ( 10 ) includes a substrate ( 12 ) having a surface; a first layer ( 14 ) of semiconductor material that is disposed above the surface, the first layer containing a first dopant at a first concentration for having a first type of electrical conductivity; and a second layer ( 16 ) of semiconductor material overlying the first layer. The second layer contains a second dopant at a second concentration for having a second type of electrical conductivity and forms a first p-n junction ( 15 ) with the first layer. The second layer is compositionally graded through at least a portion of a thickness thereof from wider bandgap semiconductor material to narrower bandgap in a direction away from the p-n junction. The compositional grading can be done in a substantially linear fashion, or in a substantially non-linear fashion, e.g., in a stepped manner. Preferably the first dopant concentration is at least an order of magnitude greater than the second concentration, and more preferably is at least two orders of magnitude greater. When the first p-n junction is reverse biased, a depletion region ( 17 ) exists substantially only within the second layer, and varying the magnitude of the reverse bias shifts the wavelength at which a maximum spectral sensitivity or responsiveness is obtained. At least one electrical contact is provided for coupling the second layer to a source ( 32 ) of variable bias voltage for reverse biasing the p-n junction. As the magnitude of the bias voltage is changed a wavelength of electromagnetic radiation to which the photodetector is responsive is thus changed. An alternating current signal can be superimposed on the reverse DC bias voltage and a synchronous detection technique used to detect photons corresponding to a certain bandgap energy.

Resistive donor-doped SrTiO3 sensors: I, basic model for a fast sensor response

Abstract: In contrast to dense donor-doped SrTiO3 (STO) ceramics and single crystals, porous fine grained thick films reveal a surprisingly fast resistivity response in reply to a change of the oxygen partial pressure (pO2) within some 10 ms even at temperatures below 900 °C. Although this unexpected behavior was attributed to a grain boundary effect, the resistivity versus pO2 plot shows a similar characteristic as found for dense ceramics or single crystals, respectively. This observation suggests that cation vacancies, which significantly influence the electrical behavior of the bulk, but which are known to equilibrate only at highest temperatures, may also play a key role in the formation of resistive grain boundaries in the moderate temperature range. For mobility reasons, a change in the cation vacancy concentration might then be limited to a few monolayers on each side of the interface and a very high interface density of defect states is needed to explain the drastic resistivity change of the sensor observed in the experiment. We propose a generalized point defect model that involves the formation of a near-interface space charge region. The latter is found to affect the local defect equilibria significantly. As a consequence, the concentration of each defect type differs from the bulk value. The fast sensor response might then originate from a space charge induced increase of the cation vacancy concentration situated only near the interface that exceeds the value predicted from electroneutral defect considerations by 2 orders of magnitude. The local formation of cation vacancies causes a strong depletion of electrons. The space charge itself is formed due to the difference in mobilities of ionic and electronic species.

Equilibrium Point Defect and Electronic Carrier Distributions near Interfaces in Acceptor-Doped Strontium Titanate

Abstract: A mathematical model based on Frenkel's theory for charged defect segregation at interfaces is used to calculate the equilibrium grain boundary depletion layer widths and conductivity profiles in acceptor-doped SrTiO3 ceramics. The calculations examine the effect of oxygen vacancy equilibration during annealing at moderate temperatures (∼1000 K) on the development of interfacial charge that influences grain boundary electrical properties at lower temperatures. Good agreement is demonstrated between the model predictions and experimental results reported in the literature.

Theory of ion beam induced charge measurement in semiconductor devices based on the Gunn's theorem

Abstract: Ion beam induced charge collection (IBIC) is a powerful experimental technique to characterise semiconductor materials and devices. It is based on the measurement of the charge induced in a given electrode by the motion of charge carriers generated by MeV ions. The problem of IBIC pulse formation is usually solved by the Shockley–Ramo theorem in which charge carriers are moving in presence of an electric field and all the electrodes are maintained at constant potentials. This theoretical model was demonstrated according to basic electrostatic principles and was first applied to evaluate the induced currents in vacuum tubes and then in semiconductor devices even in presence of stationary space charge. However, the basic assumption underlying such theorems is the independence of the space charge distribution on the applied bias voltage. Such a hypothesis is clearly not valid in partially depleted semiconductor devices where the extension of the depletion region depends on the conditions of the boundary electrodes. We present in this paper a new theoretical approach based on a general expression for electrostatic induction deduced by J.B. Gunn in 1964, which overcomes any limitation on space charge distribution. The resulting simple new formalism reduces to the Ramo–Shockley theorem as a special case. In order to clarify this theoretical approach, some simple IBIC experiments on semiconductor p–n and Schottky diodes are presented and discussed.

Approximate analytical solution to the space charge problem in nanosized Schottky diodes

Abstract: An analysis is given of the space charge region that is induced in a semiconductor by a circular Schottky contact Using the depletion approximation, the resulting free-boundary problem for Poisson’s equation is formulated and approximately solved in oblate spheroidal coordinates Expressions are derived for the boundary of the space charge region and the related depletion potential Calculations of the thickness of the Schottky barrier as a function of the diode size, down to the nanometer range, show good agreement with published results obtained numerically

Using high-k dielectrics in isolation structures method, pixel and imager device

Abstract: An imager device that has an isolation structure such that pinned photodiode characteristics are maintained without increasing doping levels. The invention provides an isolation structure to maintain pinned photodiode characteristics without increasing doping levels around the photodiode. By creating a substrate region surrounding the charge-collection region of the photodiode, the photodiode may be electrically isolated from the bulk substrate. This region fixes the depletion region so that it does not migrate toward the surface of the substrate or the STI region. By doing so, the region prevents charge from being depleted from the substrate and the accumulation region, reducing dark current.

Field dependent transformation of electron traps in GaN p–n diodes grown by metal–organic chemical vapour deposition

Abstract: Deep level transient Fourier spectroscopy (DLTFS) has been performed on p–n diodes of GaN. Typical deep level spectra of the various diodes realized on the same wafer demonstrate three electron trap levels, E1, E2 and E3 with activation energies of 0.59, 0.76 and 0.96 eV, respectively below the conduction band. The traps concentration of each level is highly sensitive to the applied electric field during the DLTFS measurements. As a result of repetitive DLTFS scans on the representative diode, the level E2 disappears after the fourth scan, while the associated peak height of the levels E1 and E3 exhibit an overall reduction by a factor of two. We correlate this effect to the transformation of electrically active charged defects into inactive ones under the influence of the electric field, which is increased in the depletion zone by the applied reverse bias. Possible inactivation mechanisms and origins of the observed levels are discussed.

PN diode optical modulators fabricated in strip loaded waveguides

Abstract: High speed optical modulators can be made of a lateral PN diode formed in a strip loaded optical waveguide on a SOI or other silicon based substrate. A PN junction is formed at the boundary of the P and N doped regions. The depletion region at the PN junction overlaps with the center of a guided optical mode propagating through the waveguide. Electrically modulating a lateral PN diode causes a phase shift in an optical wave propagating through the waveguide. Due to differences in fabrication methods, forming strip loaded waveguides with consistent properties for use in PN diode optical modulators is much easier than fabricating similar rib waveguides.

Wide range dielectric spectroscopy of ZnO-based varistors as a function of sintering time

Abstract: Broadband electrical response analysis and charge transport theory through double Schottky barriers in ceramic semiconductors, are both used in order to separately study the grain boundary, depletion layer, and bulk grain regions of ZnO-based varistor samples sintered at 1180 °C for 0 h (no significant time at the sintering temperature), 2, 4, and 8 h. It is found that increased sintering times: (1) do not sensitively affect the bulk grain region; (2) broaden and flatten the space-charge-related dielectric loss term; and (3) make disappear a particular interface trap, deep below the equilibrium Fermi level, hence modifying the grain boundary density of states.

Lateral high-voltage junction device

Abstract: A lateral high-voltage junction device (32) for over-voltage protection of an MOS circuit includes a substrate (38) having a first junction region (50) separated from a second junction region (52) by a substrate region. An MOS gate electrode (42) overlies the substrate region and is separated therefrom by a gate dielectric layer (44). Sidewall spacers (46) reside adjacent to opposing sides of the MOS gate electrode and overlie the substrate region. The substrate region is defined by a junction-free semiconductor region between the first and second junction regions. An input protection circuit (89) employs the lateral high-voltage junction device to transfer voltage transients to a ground node (94).

Semiconductor device having two different operation modes employing an asymmetrical buried insulating layer and method for fabricating the same

Abstract: According to some embodiments, a semiconductor device includes a lower semiconductor substrate, an upper silicon pattern, and a MOS transistor. The MOS transistor includes a body region formed within the upper silicon pattern and source/drain regions separated by the body region. A buried insulating layer is interposed between the lower semiconductor substrate and the upper silicon pattern. A through plug penetrates the buried insulating layer and electrically connects the body region with the lower semiconductor substrate, the through plug positioned closer to one of the source/drain regions than the other source/drain region. At least some portion of the upper surface of the through plug is positioned outside a depletion layer when a source voltage is applied to the one of the source/drain regions, and the upper surface of the through plug is positioned inside the depletion layer when a drain voltage is applied to the one region.

Schottky-barrier tunneling transistor

Abstract: A three-terminal semiconductor transistor device comprises a base region formed by a semiconductor material of a first conductivity type at a first concentration, the base region being in contact with a first electrical terminal via a semiconductor material of the second conductivity type at a second concentration, wherein the second concentration is lower than the first concentration. The three-terminal semiconductor transistor device also includes a conductive emitter region in contact with the semiconductor base region, forming a first Schottky barrier junction at the interface of the conductive emitter region and the semiconductor base region. The conductive emitter region is in contact with a second electrical terminal. The three-terminal semiconductor transistor device further includes a conductive collector region in contact with the semiconductor base region, which forms a second Schottky barrier junction at the interface of the conductive collector region and the semiconductor base region. The conductive collector region is in contact with a third electrical terminal. The tunneling current through the first Schottky barrier junction or the second Schottky barrier junction is substantially controlled by the voltage of the semiconductor base region.