Showing papers on "Design for testing published in 2018"

Testable Design of Reversible Circuits Using Parity Preserving Gates

Abstract: Editor’s note: This paper proposes an efficient design for testability technique for reversible logic circuits, which promises ultralow energy computation. — Shreyas Sen, Purdue University

Hardware Protection via Logic Locking Test Points

Abstract: Growing reverse-engineering attempts to steal or violate a design intellectual property (IP), or to identify the device technology in order to counterfeit integrated circuits (ICs), raise serious concerns in the IC design community. As the information derived from these practices can be used in a number of malicious ways, various active techniques have been proposed and deployed to protect IP, of which logic locking is a vital part. It allows inserting certain gates in a circuit’s data path to lock outputs to fixed logic values, if a wrong unlocking key is applied. This paper demonstrates that test points—industry-proven design-for-test technology used primarily to enhance the overall design testability–can also be reused in the mission mode to lock the circuit, and thus to improve the hardware security against IP piracy. In particular, it is shown that test points can facilitate the hiding of design functionality from adversaries. As a result, not only is the overall design testability improved, but also effective protection against piracy through unauthorized excess production and other forms of IP theft is ensured. Experimental results on industrial designs with test points demonstrate that the proposed scheme is effective in achieving a desired degree of hardware obfuscation.

Parallel–Series Multiobjective Genetic Algorithm for Optimal Tests Selection With Multiple Constraints

Abstract: It is known that optimal tests selection is an important issue in design for testability field. The selection is subjected to constraints of testability metrics. At the same time, test time and economic costs need to be minimized. The tests selection is a combinatorial multiobjective optimization problem. According to the schema theory, the more the amount of testability constraints, the more the constraints are violated. Therefore, the canonical genetic algorithm (GA) evolves slowly, and the Pareto-optimal solutions are less likely to be found. Based on these considerations, a parallel-series multiobjective GA (PSMOGA) is proposed. First, each test procedure is handled by a submultiobjective GA (MOGA) independently. The chromosome length of the $i$ th sub-MOGA is equal to the available tests number of the $i$ th test procedure. The sub-MOGAs are executed in parallel. The Pareto-optimal solutions to every procedure are saved for further process. Second, the MOGA is used to handle the optimal test selection problem for the whole product. The length of the chromosome is equal to the amount of the test procedures. The $i$ th gene can vary between one and $k_{i}$ , where $k_{i}$ is the solution amount of the $i$ th procedure. The genetic material from the subproblem will not be changed. Hence, the subconstraints will never be violated in the MOGA. The effectiveness and efficiency of the proposed method are verified by statistical experiments.

Design-for-testability for continuous-flow microfluidic biochips

Abstract: Flow-based microfluidic biochips are gaining traction in the microfluidics community since they enable efficient and low-cost biochemical experiments. These highly integrated lab-on-a-chip systems, however, suffer from manufacturing defects, which cause some chips to malfunction. To test biochips after manufacturing, air pressure is applied to input ports of a chip and predetermined test vectors are used to change the states of microvalves in the chip. Pressure meters are connected to the output ports to measure pressure values, which are compared with expected values to detect errors. To reduce the cost of the test platform, the number of pressure sources and meters should be reduced. We propose a design-for-testability (DFT) technique that enables a test procedure with only a single pressure source and a single pressure meter. Furthermore, the valves inserted for DFT share control channels with valves in the original chip so that no additional control signals are required. Simulation results demonstrate that this technique can generate efficient chip architectures for single-source single-meter test in all experiment cases successfully to reduce test cost, while the performance of these chips in executing applications is still maintained.

A Built-in Self-Test Scheme for Detecting Defects in FinFET-Based SRAM Circuit

Abstract: FinFET is a feasible solution to short-channel effects that has been encountered by planar transistors during process scaling, and is widely adopted in advanced CMOS technologies. However, the special physical structure of FinFET also brings new defect models, which are hard to detect by conventional March algorithms, thus a more effective test methodology is required. In this paper, we investigate defect candidates in a FinFET 6T-SRAM circuit, analyze their fault behaviors, and propose a built-in self-test (BIST) scheme to enhance fault coverage and reduce test time. The proposed BIST approach is able to detect all target defects with only one read cycle, which reduces the required test algorithm complexity and hence reduces test time. This BIST scheme can be used with classical March algorithms, such as the March C-, to extend fault coverage beyond static single cell or coupling faults, thus reducing the defect level.

Time-Multiplexed 1687-Network for Test Cost Reduction

Abstract: The reconfigurable scan network standardized by IEEE std. 1687 offers flexibility in accessing the on-chip instruments, which significantly improves the test cost. In this paper, we present a novel time-multiplexed 1687-network architecture that significantly improves the absolute test application time of systems-on-chip at wafer-level as well as package-levels tests. This architecture leverages: 1) the ever increasing tester channel frequency; 2) the allowed test frequencies at the two test levels; and 3) the flexibility offered by the 1687-network. We also present a test-time calculation method for the proposed network architecture and use it in our experiments. Furthermore, we study the effects of the number of time slots on different parameters.

A High Performance Scan Flip-Flop Design for Serial and Mixed Mode Scan Test

Abstract: Over the years, serial scan design has become the de-facto design for testability technique. The ease of testing and high test coverage has made it gain widespread industrial acceptance. However, there are penalties associated with the serial scan design. These penalties include performance degradation, test data volume, test application time, and test power dissipation. The performance overhead of scan design is due to the scan multiplexers added to the inputs of every flip-flop. In today’s very high-speed designs with minimum possible combinational depth, the performance degradation caused by the scan multiplexer has become magnified. Hence, to maintain circuit performance, the timing overhead of scan design must be addressed. In this paper, we propose a new scan flip-flop design that eliminates the performance overhead of serial scan. The proposed design removes the scan multiplexer from the functional path. The proposed design can help improve the functional frequency of performance critical designs. Furthermore, the proposed design can be used as a common scan flip-flop in the “mixed scan” test wherein it can be used as a serial scan cell as well as a random access scan (RAS) cell. The mixed scan test architecture has been implemented using the proposed scan flip-flop. The experimental results show a promising reduction in interconnect wire length, test time, and test data volume, compared to the state-of-the-art RAS and multiple serial scan implementations.

Challenges and solutions for high-volume testing of silicon photonics

Abstract: The first generation of silicon photonic products is now commercially available. While silicon photonics possesses key economic advantages over classical photonic platforms, it has yet to become a commercial success because these advantages can be fully realized only when high-volume testing of silicon photonic devices is made possible. We discuss the costs, challenges, and solutions of photonic chip testing as reported in the recent research literature. We define and propose three underlying paradigms that should be considered when creating photonic test structures: Design for Fast Coupling, Design for Minimal Taps, and Design for Parallel Testing. We underline that a coherent test methodology must be established prior to the design of test structures, and demonstrate how an optimized methodology dramatically reduces the burden when designing for test, by reducing the needed complexity of test structures.

Design for Stuck-at Fault Testability in MCT based Reversible Circuits

Abstract: Testability leads to a large increment in operating costs from their original circuits which drastically increases the power consumption in logic circuits. This paper presents a new design for testability methodology for the detection of stuck-at faults in multiple controlled Toffoli based reversible circuits. The circuit is modified in such a manner that the applied test vector reaches all the levels without any change in values on the wires of the circuit. An (n+1) dimensional general test set containing only two test vectors is presented, which provide full coverage of single and multiple stuck-at faults in the circuit. The work is further extended to locate the occurrence of stuck-at faults in the circuit. Deterministic approaches are described and the modification methodology is experimented on a set of benchmarks. The present work achieved a reduction up to $50.58\%$ in operating costs as compared to the existing work implemented on the same platform.

Oscillation-based DFT for Second-order Bandpass OTA-C Filters

Abstract: This paper describes a design for testability technique for second-order bandpass operational transconductance amplifier and capacitor (OTA-C) filters using an oscillation-based test topology. The oscillation-based test structure is a vectorless output test strategy easily extendable to built-in self-test. The proposed methodology converts filter under test into a quadrature oscillator using very simple techniques and measures the output frequency. Using feedback loops with nonlinear block, the filter to oscillator conversion techniques easily convert the bandpass OTA-C filter into an oscillator. With a minimum number of extra components, the proposed scheme requires a negligible area overhead. The validity of the proposed method has been verified using comparison between faulty and fault-free simulation results of Tow-Thomas and KHN OTA-C filters. Simulation results in 0.25 $$\upmu $$ m CMOS technology show that the proposed oscillation-based test strategy for OTA-C filters is suitable for catastrophic and parametric faults testing and also effective in detecting single and multiple faults with high fault coverage.

IDDQ Testing of Low Voltage CMOS Operational Transconductance Amplifier

Abstract: The paper describes the design for testability (DFT) of low voltage two stage operational transconductance amplifiers based on quiescent power supply current (IDDQ) testing. IDDQ testing refers to the integral circuit testing method based upon measurement of steady state power supply current for testing both digital as well as analog VLSI circuit. A built in current sensor, which introduces insignificant performance degradation of the circuit-under-test, has been proposed to monitor the power supply quiescent current changes in the circuit under test. Moreover, the BICS requires neither an external voltage reference nor a current source and able to detect, identify and localize the circuit faults. Hence the BICS requires less area and is more efficient than the conventional current sensors. The testability has also been enhanced in the testing procedure using a simple fault-injection technique. Both bridging and open faults have been analyzed in proposed work by using n-well 0.18µm CMOS technology.

Educational design kit for synopsys tools with a set of characterized standard cell library

Abstract: ON Semiconductor 500 nm process (ONC5) is a well establish technology for educational IC development. However a full design flow in native rules is not offered for Synopsys tools. This paper describes the construction of an Educational Process Design Kit (PDK) with full digital and analog flow, Standard cell library and Special Cells. The PDK includes a library of 100 characterized standard cells, which supports clock gating and design for testability techniques that allow fast digital IC development. It also has a set of Parametric Python Cells for analog development. These components of the PDK improve any type of mixed-signal design for educational and research purposes.

Clock-Less DFT-Less Test Strategy for Null Convention Logic

Abstract: Null Convention Logic (NCL) is a robust asynchronous technique that poses new challenges to test and testability strategies due to the lack of a clock signal and the state-holding behavior of the NCL gates. The lack of deterministic timing in NCL complicates the management of test timing, and stuck-at faults on gate internal feedback (GIF) of the NCL gates exhibit a totally different effect compared to that of stuck-at faults on the gate inputs. Stuck-at faults on gate internal feedback of NCL gates do not always cause an incorrect output and therefore are considered hard-to-detect or undetectable by automatic test pattern generation (ATPG) algorithms. Such faults could leave the primary outputs of the circuit completely unaffected or sometimes they only affect the circuit by early detection of completeness. This work first proposes a clock-less self-timed ATPG, with no added design for test (DFT), that detects all of the faults on the gate inputs and a share of those on the GIF of gates. Then, this work investigates the effectiveness of I_DDQ (quiescent current) test for detecting stuck-at faults on GIF of NCL gates. Hspice is used for implementing static and semi-static transistor-level NCL gates in (45 nm, 1.1 V) technology, for which the supply current is measured and compared for fault-free and faulty circuits. The experimental results show that the faulty current is orders of magnitude higher than the fault-free leakage current. This considerable difference shows that I_DDQ testing might be an efficient and low-cost candidate for detecting stuck-at faults on GIF of NCL gates. The proposed I_DDQ test method along with the self-timed ATPG has resulted in average 98.16 and 98.04 percent fault coverage for static and semi-static implementations of several NCL circuits, respectively. To the extent of our knowledge, this is the first work that has addressed clock-less, self-timed ATPG for NCL with no area overhead, and also the first work conducted on I_DDQ test for NCL.

Fault tolerant system based on IDDQ testing

Abstract: Offline test is essential to ensure good manufacturing quality. However, for permanent or transient faults that occur during the use of the integrated circuit in an application, an online integrated test is needed as well. This procedure should ensure the detection and possibly the correction or the masking of these faults. This requirement of self-correction is sometimes necessary, especially in critical applications that require high security such as automotive, space or biomedical applications. We propose a fault-tolerant design for analogue and mixed-signal design complementary metal oxide (CMOS) circuits based on the quiescent current supply (IDDQ) testing. A defect can cause an increase in current consumption. IDDQ testing technique is based on the measurement of power supply current to distinguish between functional and failed circuits. The technique has been an effective testing method for detecting physical defects such as gate-oxide shorts, floating gates (open) and bridging defects in...

Scan-based side channel attack on stream ciphers and its prevention

Abstract: Scan chains, a design for testability feature, are included in most modern-day ICs. But, it opens a side channel for attacking cryptographic chips. We propose a methodology by which we can recover internal states of any stream cipher using scan chains. We consider conventional scan chain design which is normally not scrambled or protected in any other way. In this scenario, the challenge of the adversary is to obtain the correspondence of output of the scan chain and the internal state registers of the stream cipher. We present a mathematical model of the attack and the correspondence between the scan chain-outputs and the internal state bits have been proved under this model. We propose an algorithm that through offline and online simulation forms bijection between the above-mentioned sets and thus finds the required correspondence. We also give an estimate of the number of offline simulations necessary for finding the correspondence. The proposed strategy is successfully applied to eStream hardware based winners MICKEY-128 2.0, Trivium and Grain-128.

A Software Based on Multi-Signal Flow Graph Model for PHM-Oriented Design for Testability

Abstract: This paper introduced a new software named Design and Analysis System for Testability Engineering (DASTE)developed for PHM-oriented design for testability (DFT)aiming at assisting developers improve their designs. First, we developed a visual development environment based on multi-signal flow graph model. Second, we got a failure-test dependency matrix by analyzing the relationship between failures and symptoms, and the relationship between tests and symptoms. Next, we analyzed the testability indices according the dependency matrix and fault propagation time. Last, an amplifier circuit as an example is used to verify the function of the DASTE.

Test Time Reduction on Testing Delay Faults in 3D ICs Using Boundary Scan Design

Abstract: A boundary scan design with embedded time-to-digital converter (TDCBS) has been proposed for testing small delay faults. In this paper, the TDCBS is applied for testing TSVs in 3D IC. To reduce test application time of the TDCBS, we propose a modified TAP controller that utilizes the bypass mode for reducing unnecessary scan shifts during observation of the captured results. The simulation for an experimental circuit is shown to evaluate the effectiveness of the proposed method.

DFT methodologies for testing k-CNOT, Fredkin and Peres based reversible circuits

Abstract: The widespread use of reversible logic for low-power and high-speed applications has made testing of reversible circuits a primary focus for researchers in order to ensure the manufacture of highly reliable circuits. In this work, we propose two methods to convert a given Reversible Circuit (RC) into a testable RC. Initially, we present the modification to ESOP (EXOR Sum of Product) based online testing methodology with additional test vectors to detect the wide class of faults in RC designed with k-CNOT, Fredkin and Peres gates. Then, we propose a new Design for Testability (DFT) technique which effectively detects various faults, using a minimum test set for higher fault coverage with additional DFT hardware. The proposed methodologies are validated on various reversible benchmark circuits and comparison of fault coverage and hardware overhead are compared with that of existing approaches.

Computer-Aided Design of Microfluidic Very Large Scale Integration (mVLSI) Biochips : Design Automation, Testing, and Design-for-Testability

Abstract: This book provides a comprehensive overview of flow-based, microfluidic VLSI. The authors describe and solve in a comprehensive and holistic manner practical challenges such as control synthesis, wash optimization, design for testability, and diagnosis of modern flow-based microfluidic biochips. They introduce practical solutions, based on rigorous optimization and formal models. The technical contributions presented in this book will not only shorten the product development cycle, but also accelerate the adoption and further development of modern flow-based microfluidic biochips, by facilitating the full exploitation of design complexities that are possible with current fabrication techniques.

Weak Cell Detection Techniques for Memristor-Based Memories

Abstract: By virtue of its non-linear switching characteristics manifested by ionic percolation in the solid lattice under the influence of applied voltage, memristor is regarded as non-volatile memory (NVM) otherwise known as resistive random access memory (RRAM). It possesses promising characteristics such as low power, non-volatility, high density and multi-level functions to replace the present CMOS gates and memories. Nevertheless, it is greatly affected by process variations, particularly variation in thickness. Fault analysis proves that there are number of stability faults occur in addition to other typical memory faults. This research work presents a novel built-in self-test techniques to test the weak memory cells in memristor memory arrays. The basic idea is to create electrical stress to the cells such that the strong cells will retain its state while the weak cells expected to flip its state. Most of the design for testability (DFT) techniques employ the deterministic test patterns algorithm like March tests. Though March tests are very effective for the conventional memories, they are not so effective in case of memristor-based memories. Stability faults such as the undefined state faults cannot be sensitized using the conventional March test patterns. Thus, to enhance the fault coverage, new weak read and weak write mode approaches namely short refresh time (SRT), short write time (SWT) and low write voltage (LWV) are to be employed in the test sequence. Cadence Spectre gpdk180 library and memristor linear ion drift model with Biolek window function were used to perform the stability fault injection and circuit functional simulation.

More than a timing resilient template: a case study on reliability-oriented improvements on blade

Abstract: As the VLSI design moves into ultra-deep-submicron technologies, timing margins added due to variabilities in the manufacturing process, operation temperature and supply voltage become a significant part of the clock period in traditional synchronous circuits. Timing resilient architectures emerged as a promising solution to alleviate these worst-case timing margins, improving system performance and/or reducing energy consumption. These architectures embed additional circuits for detecting and recovering from timing violations that may arise after designing the circuit with reduced time margins. Asynchronous systems, on the other hand, have a potential to improve energy efficiency and performance due to the absence of a global clock. Moreover, asynchronous circuits are known to be robust to process, voltage and temperature variations. Blade is an asynchronous timing resilient template that leverages the advantages of both asynchronous and timing resilient techniques. However, Blade still presents challenges regarding its testability, which hinders its commercial or large-scale application. Although the design for testability with scan chains is widely applied in the industry, the high silicon costs associated with its use in Blade can be prohibitive. Asynchronous circuits can also present advantages for functional testing, and the timing resilient characteristic provides continuous feedback during normal circuit operation, which can be applied for concurrent testing. In this Thesis, Blade’s testability is evaluated from a different perspective, where circuits implemented with Blade present reliability properties that can be explored for stuck-at and delay faults testing. Initially, a fault classification method that relates behavioral patterns with structural faults inside the error detection logic and a new test-driven implementation of this detection module are proposed. The control part is analyzed for internal faults, and a new design is proposed, where the test coverage is improved and the circuit can be further optimized by the design flow. An original method for time measuring delay lines is also addressed. Finally, delay fault testing of critical paths in the data path is explored as a natural consequence of a Blade circuit, where the continuous monitoring for detecting timing violations provide the necessary feedback for online detection of these delay faults. The integration of all the contributions provides a satisfactory fault coverage for an area overhead that, for the evaluated circuits in this thesis, can vary from 4.24% to 6.87%, while the scan approach for the same circuits implies an area overhead varying from 50.19% to 112.70%, respectively. The contributions of this Thesis demonstrated that with a few improvements in the Blade architecture it is possible to expand its reliability beyond a timing resilient system to delay violations in the data path, but also advances for fault testing (including online faults) of the entire circuit, yield, and aging.

A novel efficient TSV built-in test for stacked 3D ICs

Abstract: A through-silicon via (TSV) is established as the main enabler for a three-dimensional integrated circuit (3D IC) that increases system density and compactness. The exponential increase in TSV density led to TSV-induced catastrophic and parametric faults. We propose an original architecture that detects errors caused by TSV manufacturing defects. The proposed design for testability is a built-in technique that detects errors in an early manufacturing stage and is hence very economically attractive. The proposal is capable of testing each and every TSV in the network. The technique achieves high fault coverage and high observability.

Handling Unknown with Blend of Scan and Scan Compression

Abstract: In scan compression, all scannable Flip-Flops are part of internal scan channels connected between Decompressor and Compressor. The capture-X (unknown values in the test response) in the Flip-Flops after capture cycle of scan synthesis, results in loss of coverage and/or pattern inflation when masking is used to block the Xs irrespective of the X-masking techniques used in scan compression. In this paper, we exploited this potential and propose a hybrid DFT (Design For Testability) architecture to achieve better compression and reduce patterns count. This is a mixture of an external scan chain and scan compression. A methodology has been put in place based on the potential of a capture-X value of occurring in Flip-Flips, to find out which Flip-Flops (scan cells) should be part of the internal scan channels (chains) between Decompressor and Compressor, and which Flip-Flops should be put outside the codec (Compressor-Decompressor) as an external scan chain. The results show the benefits of the hybrid architecture which is shown to bring significant improvement in pattern count.

Apparatus and method for implementing design for testability (DFT) for bitline drivers of memory circuits

Abstract: A first bitline driver includes a multiplexer for outputting data and write mask signals in functional mode, and test vector signal in test mode; a latch to latch the data signal in functional mode and the test vector signal in test mode; a latch to latch the write mask signal in functional mode and the test vector signal in test mode; a latch to latch the test vector signal and provide it to a scan output; and a write circuit for writing data to a memory cell based on the data signal A second bitline driver includes a latch to latch a data signal in functional mode if a write mask signal is deasserted and to latch a test vector signal in test mode; a latch to latch the test vector signal and provide it to a scan output; and a write circuit for writing data to a memory cell

ADAGE: Automatic DfT-Assisted Generation of Test Stimuli for Mixed- Signal Integrated Circuits

Abstract: This paper presents an integrated workflow for design-for-test and test signal generation of mixed-signal circuits. The DfT phase pre-partitions the core under test and allows an efficient automatic generation of test signals. —Hans-Joachim Wunderlich, Universitat Stuttgart

A Novel Countermeasure Against Differential Scan Attack in AES Algorithm

Abstract: The Design for Testability (specifically scan designs) is standard testing techniques for Digital cores for achieving high fault coverage and to provide better controllability and observability. However, such test architectures in the chip containing secret data mostly becomes the instrumental for secret information leakage. The attacker may use different implementation attacks to leak the secret data. In this paper, we first analyse the existing scan designs from security perspective. We demonstrated that how the secret key is retrieved by differential scan attack (DSA) in case of symmetric encryption standards (AES). Furthermore, it is also shown that AES along with time compactor also fails to provide sufficient security. We then propose novel prevention mechanism, Modular Exponentiation Secure Scheme (ME-SS), which clears the insecure states of all the existing techniques. Our experimental results show that the proposed countermeasures can effectively insulate all the information related to cipher key from DSA.

Software-Based Self-Test with Decision Diagrams for Microprocessors

Abstract: The field of Software-Based Self-Test (SBST) has been a topic of extensive research in industry and academia for more than three decades. Despite that an automated self-test generation is still lacking a suitable formalisation for modeling of microprocessors. This book presents a methodology to formalize and automate SBST synthesis and is leading to a reassessment of microprocessor modeling process. The book consists of four logically connected parts, starting with state-of-the-art in the field of SBST and with introductory material on modelling methods. The following parts narrate the problems of microprocessor model synthesis, high-level fault modeling, test data generation, and self-test test program construction. Based on the ground set in the first two parts, the book presents methods of automation of model synthesis and self-test program synthesis. Final part completes the research, incorporating the SBST programs into testing flow of processor-centric boards. The book is intended for use by CAD and test engineers, researchers, graduate students, or as supplementary material for courses on computer architectures, and test or design for testability of digital systems.