Showing papers on "Electronic design automation published in 2002"

Managing power and performance for system-on-chip designs using Voltage Islands

Abstract: This paper discusses Voltage Islands, a system architecture and chip implementation methodology, that can be used to dramatically reduce active and static power consumption for System-on-Chip (SoC) designs. As technology scales for increased circuit density and performance, the need to reduce power consumption increases in significance as designers strive to utilize the advancing silicon capabilities. The consumer product market further drives the need to minimize chip power consumption. Effective use of Voltage Islands for meeting SoC power and performance requirements, while meeting Time to Market (TAT) demands, requires novel approaches throughout the design flow as well as special circuit components and chip powering structures. This paper outlines methods being used today to design Voltage Islands in a rapid-TAT product development environment, and discusses the need for industry EDA advances to create an industry-wide Voltage Island design capability.

Real-Time Design Patterns: Robust Scalable Architecture for Real-Time Systems

Abstract: When creating real-time and embedded (RTE) systems, there is no room for error. The nature of the final product demands that systems be powerful, efficient, and highly reliable. The constraints of processor and memory resources add to this challenge. Sophisticated developers rely on design patterns-proven solutions to recurrent design challenges-for building fail-safe RTE systems.Real-Time Design Patterns is the foremost reference for developers seeking to employ this powerful technique. The text begins with a review of the Unified Modeling Language (UML) notation and semantics then introduces the Rapid Object-Oriented Process for Embedded Systems (ROPES) process and its key technologies. A catalog of design patterns and their applications follows.Key topics covered in this book include: Identifying large-scale strategic decisions that affect most software elements Coordinating and organizing system components and subsystems Managing memory and resources Defining how objects can be distributed across multiple systems Building safe and reliable architectures Mapping subsystem and component architectures to underlying hardwareThe book's extensive problem-solving templates, which draw on the author's years in the trenches, will help readers find faster, easier, and more effective design solutions.The accompanying CD-ROM contains: Related papers Object Management Group (OMG) specifications Rhapsody™-a UML-compliant design automation tool that captures the analysis and design of systems and generates full behavioral code with intrinsic model-level debug capabilities RapidRMA™-a tool that integrates with Rhapsody™ to perform schedulability and timeliness analysis of UML models 0201699567B08142002

PICO: automatically designing custom computers

Abstract: The paper discusses the PICO (program in, chip out) project, a long-range HP Labs research effort that aims to automate the design of optimized, application-specific computing systems - thus enabling the rapid and cost-effective design of custom chips when no adequately specialized, off-the-shelf design is available. PICO research takes a systematic approach to the hierarchical design of complex systems and advances technologies for automatically designing custom nonprogrammable accelerators and VLIW processors. While skeptics often assume that automated design must emulate human designers who invent new solutions to problems, PICO's approach is to automatically pick the most suitable designs from a well-engineered space of designs. Such automation of embedded computer design promises an era of yet more growth in the number and variety of innovative smart products by lowering the barriers of design time, designer availability, and design cost.

Logic Synthesis for Asynchronous Controllers and Interfaces

Abstract: This book is devoted to logic synthesis and design techniques for asynchronous circuits. It uses the mathematical theory of Petri Nets and asynchronous automata to develop practical algorithms implemented in a public domain CAD tool. Asynchronous circuits have so far been designed mostly by hand, and are thus much less common than their synchronous counterparts, which have enjoyed a high level of design automation since the mid-1970s. Asynchronous circuits, on the other hand, can be very useful to tackle clock distribution, modularity, power dissipation and electro-magnetic interference in digital integrated circuits. This book provides the foundation needed for CAD-assisted design of such circuits, and can also be used as the basis for a graduate course on logic design.

Spacedesign: a mixed reality workspace for aesthetic industrial design

Abstract: Spacedesign is an innovative mixed reality (MR) application addressed to aesthetic design of free form curves and surfaces. It is a unique and comprehensive approach which uses task-specific configurations to support the design workflow from concept to mock-up evaluation and review. The first-phase conceptual design benefits from a workbench-like 3-D display for free hand sketching, surfacing and engineering visualization. Semitransparent stereo glasses augment the pre-production physical prototype by additional shapes, textures and annotations. Both workspaces share a common interface and allow collaboration and cooperation between different experts, who can configure the system for the specific task. A faster design workflow and CAD data consistency can be thus naturally achieved. Tests and collaborations with designers, mainly from automotive industry, are providing systematic feedback for this ongoing research. As far as the authors are concerned, there is no known similar approach that integrates the creation and editing phase of 3D curves and surfaces in virtual and augmented reality (VR/AR). Herein we see the major contribution of our new application.

Coping with latency in SOC design

Abstract: Latency-insensitive design is the foundation of a correct-by-construction methodology for SOC design. This approach can handle latency's increasing impact on deep-submicron technologies and facilitate the reuse of intellectual-property cores for building complex systems on chips, reducing the number of costly iterations in the design process.

Sub-90 nm technologies-challenges and opportunities for CAD

Abstract: Future high performance microprocessor design with technology scaling beyond 90 nm will pose two major challenges: (1) energy and power, and (2) parameter variations. Design practice will have to change from deterministic design to probabilistic and statistical design. This paper discusses circuit techniques and design automation opportunities to overcome the challenges.

Proceedings : 2002 Design, Automation and Test in Europe, conference and exhibition : March 4-8, 2002, Paris, France

Abstract: This volume originated from the 2002 Design, Automation and Test in Europe Conference and Exhibition, and examines computer hardware design and testing. It is aimed at researchers, professors, practitioners and students.

Pipe-routing algorithm development: case study of a ship engine room design

Abstract: This study presents an automatic pipe-routing algorithm accommodating all major detail-design facets. First, the algorithm uses pattern-match methods to provide candidate paths. A cell-generation method is developed which satisfies geometric constraints. This makes the generation and evaluation of paths effective and efficient. Next, various non-geometric aspects, such as material costs, installation costs, and valve operability, are assessed from a fiscal point of view. Then, from a tree of combinations, the algorithm chooses an appropriate path for each pipeline from the candidate paths. Finally, a general approach toward detail design automation is suggested. The software implementation was done with Microsoft Visual Basic 6.0 and Access 2000, Heide Corporation Intent! for AutoCAD 2000, and AutoDesk AutoCAD 2000.

Designing with FPGAs and CPLDs

Abstract: From the Publisher: Choose the right programmable logic devices and development tools Understand the design, verification, and testing issues Plan schedules and allocate resources efficiently Choose the right programmable logic devices with this guide to the technologies and internal architectures of Field Programmable Gate Arrays FPGAs) and Complex Programmable Logic Devices (CPLDs). This complete reference is written in easy-to-understand language intended for engineers who are planning a CPLD-based or FPGA-based design; managers who need to plan, schedule, and budget a CPLD-based or FPGA-based design; and board-level designers who need to design CPLDs or FPGAs into a product. Experienced designers will find well-structured guidelines for future projects. The author explains the entire procedure for designing these devices from specification through production. Programmable logic devices are explained in an overview, leading up to a detailed description of CPLDs and FPGAs. The various architectures are examined thoroughly along with the tradeoffs - allowing you to decide which particular device is right for your design. Engineers learn about important design, verification, synthesis, and testing issues for producing an optimized and reliable design as well as the different Electronic Design Automation (EDA) tools available. Engineering managers learn how to use the step-by-stepUniversal Design Methodology (UDM) to optimally allocate resources and to schedule and budget the development process accurately.

Computer-Aided Design of Analog Integrated Circuits and Systems

Abstract: From the Publisher: The tools and techniques you need to break the analog design bottleneck! Ten years ago, analog seemed to be a dead-end technology. Today, System-on-Chip (SoC) designs are increasingly mixed-signal designs. With the advent of application-specific integrated circuits (ASIC) technologies that can integrate both analog and digital functions on a single chip, analog has become more crucial than ever to the design process. Today, designers are moving beyond hand-crafted, one-transistor-at-a-time methods. They are using new circuit and physical synthesis tools to design practical analog circuits; new modeling and analysis tools to allow rapid exploration of system level alternatives; and new simulation tools to provide accurate answers for analog circuit behaviors and interactions that were considered impossible to handle only a few years ago. To give circuit designers and CAD professionals a better understanding of the history and the current state of the art in the field, this volume collects in one place the essential set of analog CAD papers that form the foundation of today's new analog design automation tools. Areas covered are: Analog synthesis Symbolic analysis Analog layout Analog modeling and analysis Specialized analog simulation Circuit centering and yield optimization Circuit testing Computer-Aided Design of Analog Integrated Circuits and Systems is the cutting-edge reference that will be an invaluable resource for every semiconductor circuit designer and CAD professional who hopes to break the analog design bottleneck.

Multi-board connection system for use in electronic design automation

Abstract: A high fan-out hub array system and method is provided. The system includes at least one hub that contains user logic that receive signals from various chips and boards, and which quickly turnarounds another signal (based on the logic) out to the desired chips and boards. In a CLKGEN implementation, a global clock is generated in the hub and distributed in a high fan-out manner to all the FPGA logic chips in the system. For a bus resolution application, a hub contains bus resolution logic to resolve bus access requests. It resolves the various requests and delivers the result to all the relevant chips and boards. In a STOPWHEN application, when a STOPWHEN condition has been met, the system delivers a pause signal to all the chips and boards via the high fan-out hubs.

Intermediate Representations for Design Automation of Multiprocessor DSP Systems

Abstract: Self-timed scheduling is an attractive implementation style for multiprocessor DSP systems due to its ability to exploit predictability in application behavior, its avoidanceof over-constrained synchronization, and its simplified clocking requirements.However, analysis and optimization of self-timed systems under real-time constraintsis challenging due to the complex, irregular dynamics of self-timed operation.In this paper, we review a number of high-level intermediate representationsfor compiling dataflow programs onto self-timed DSP platforms, including representationsfor modeling the placement of interprocessor communication (IPC) operations;separating synchronization from data transfer during IPC; modeling and optimizinglinear orderings of communication operations; performing accurate design spaceexploration under communication resource contention; and exploring alternativeprocessor assignments during the synthesis process. We review the structureof these representations, and discuss efficient techniques that operate onthem to streamline scheduling, communication synthesis, and power managementof multiprocessor DSP implementations.

Neural based dynamic modeling of nonlinear microwave circuits

Abstract: A neural network formulation for modeling nonlinear microwave circuits is achieved in the most desirable format, i.e., continuous time-domain dynamic system format. The proposed dynamic neural network (DNN) model can be developed directly from input-output data without having to rely on internal details of the circuit. An algorithm is developed to train the model with time or frequency domain information. A circuit representation of the model is proposed such that the model can be incorporated into circuit simulators for high-level design. Examples of dynamic-modeling of amplifiers, mixer and their use in system simulation are presented.

System-level abstraction semantics

Abstract: Raising the level of abstraction is widely seen as the solution for closing the productivity gap in system design. They key for the success of this approach, however, are well-defined abstraction levels and models. In this paper, we present such system level semantics to cover the system design process. We define properties and features of each model. Formalization of the flow enables design automation for synthesis and verification to achieve the required productivity gains. Through customization, the semantics allow creation of specific design methodologies. We applied the concepts to system languages SystemC and SpecC. Using the example of a JPEG encoder, we will demonstrate the feasibility and effectiveness of the approach.

Self-contained embedded test design environment and environment setup utility

Abstract: An embedded test, chip design utility is an ease-of-use utility for assisting a circuit designer in quickly implementing a circuit embedded test design flow. Using the utility, a designer transforms a design netlist to include embedded test structures. The utility automatically builds a workspace containing a predetermined repository structure and design environment, generates control files for executing design automation tools that operate within the design flow, and encapsulates the data so as to be self-contained and easily transferable to other design teams.

Test vector compression using EDA-ATE synergies

Abstract: This paper presents a new test vector compression technique, which utilizes synergies between Automatic Test Pattern Generation (ATPG) tools provided by EDA (Electronic Design Automation) vendors and Automatic Test Equipment (ATE). The basic approach is to achieve significant compression by agreeing between ATE and ATPG on how to fill don't care values in the test vectors such that these bits need not be stored on ATE and also possibly not communicated to DUT if decompression is done on chip. Our new technique allows sub-vector level fine grained mixing of pseudo-randomly generated bits and ATPG generated bits. Experimental results, on an actual industrial network processor design, show a compression ratio of about 17x.

Modeling and analysis techniques for system-level architectural design of telecom front-ends

Abstract: An overview is presented of the challenges and design issues in the system-level design of mixed analog-digital telecom front-ends. The progress in very large scale integration technology allows the integration of complex systems on a chip, containing both analog and digital parts. In order to boost the design productivity and guarantee the optimality of such systems while meeting the time-to-market constraints, a systematic top-down design approach has to be followed with sufficient time and attention paid to system-level architectural design before proceeding to the detailed block or circuit design. This paper presents high-level system exploration tools that allow the analysis of architectural alternatives for the telecom front-end and to explore system tradeoffs such as finding the optimal analog-digital partitioning. This is illustrated with results from experimental tools. Finally, the crucial underlying technology for such high-level design will be described in detail: analog behavioral modeling, efficient high-level simulation methods, and analog power/area estimation.

Asynchronous circuits: an increasingly practical design solution

Abstract: While ultra-deep-submicron design presents increasingly difficult challenges for standard synchronous design practices, recent research in asynchronous design techniques is making asynchronous circuits an increasingly practical alternative. These challenges include the increasing pressure for low-power, the growing challenge of predicting increasing impact of wire load and delay, and the performance penalty associated with supporting communication between different clock domains. This paper reviews the different solutions to these problems that the spectrum of existing asynchronous design techniques support. It focuses on techniques for fine-grain two-dimensional pipelining that yield ultra-high-speed at nominal power supplies and very low-energy at reduced power supplies.

Design method and automation of comparator generation for flash A/D converter

Abstract: The design methods and the automation of the comparator circuit layout generation for a flash A/D converter are presented in this paper. The threshold inverter quantization (TIQ) based A/D converters require 2/sup n/ - 1 comparators, each one different from all others. Optimal design method of the TIQ comparator presented in this paper significantly improves the linearity of the A/D converter against the CMOS process variation. Especially the DNL dependence on the CMOS process variation can be almost eliminated. The design method has been incorporated into a software package and the 2/sup n/ - 1 optimized TIQ comparator layouts are generated as an output of the software package. The simulation results are presented to show the effectiveness of the design methods. Also, the prototype chip has been fabricated, with initial test results confirming the DNL reduction.

An introductory digital design course using a low-cost autonomous robot

Abstract: This paper describes a new digital design laboratory developed for undergraduate students in this electrical and computer engineering curriculum. A top-down rapid prototyping approach with commercial computer-aided design tools and field-programmable logic devices (FPLDs) is used for laboratory projects. Students begin with traditional transistor-transistor logic-based projects containing a few gates and progress to designing a simple 16-bit computer, using very high-speed integrated circuits hardware description language (VHDL) synthesis tools and an FPLD. To help motivate students, the simple computer design is programmed to control a small autonomous robot with two servo drive motors and several sensors. The laboratory concludes with a team-based design project using the robot.

Hybrid circuit-full-wave computer-aided design of a manifold multiplexers without tuning elements

Abstract: A hybrid procedure is introduced for computer-aided design (CAD) of manifold multiplexers without tuning elements. The procedure is based on: (1) a standard initial design with a simple network prototype; (2) a hybrid optimization with the multiplexer manifold rigorously described by a full-wave model and filters still described in terms of their network prototype; and (3) a final full-wave optimization of the entire structure. The proposed approach drastically reduces computer time while making it feasible to perform a very accurate full-wave optimization which in turn allows the avoidance of using tuning elements. An example illustrates and validates the CAD procedure.

Design of asynchronous circuits by synchronous CAD tools

Abstract: The roadblock to wide acceptance of asynchronous methodology is poor CAD support. Current asynchronous design tools require a significant re-education of designers, and their features are far behind synchronous commercial tools. This paper considers a particular subclass of asynchronous circuits (null convention logic or NCL) and suggests a design flow that is based entirely on commercial CAD tools. This new design flow shows a significant area improvement over known flows based on NCL.

Relative timing based verification of timed circuits and systems

Abstract: Aggressive timed circuits, including synchronous and asynchronous self-resetting circuits, are particularly challenging to design and verify due to complicated timing constraints that must hold to ensure correct operation. Identifying a small, sufficient, and easily verifiable set of relative timing constraints simplifies both design and verification. However, the manual identification of these constraints is a complex and error-prone process. This paper presents the first systematic algorithm to generate and optimize relative timing constraints sufficient to guarantee correctness. The algorithm has been implemented in our RTCG tool and has been applied to several real-life circuits. In all cases, the tool successfully generates a sufficient set of easily verifiable relative timing constraints. Moreover the generated constraint sets are the same size or smaller than that of the hand-optimized constraints.

PARALLEL ELECTRONIC DESIGN AUTOMATION: Distributed SIMULTANEOUS EDITING

Abstract: A method and apparatus are described for allowing multiple users to simultaneously edit a design while being able to view edits to the entire design (1404). A design (such as for printed circuit board) having a plurality of exclusive areas is displayed to a plurality of users (1402). A first user checks out a corresponding section of the design, and edits the design (1406), A second user checks out a corresponding section of the design, and edits the design simultaneously with the first user editing the design (1406).

Parallel Electronic Design Automation: Shared Simultaneous Editing

Abstract: A method to simultaneously allow multiple users to edit in shared areas of a master design includes displaying the master design, allowing a first user to edit in a shared area of the design, while simultaneously allowing a second user to edit in a shared area of the design while preserving the integrity of the design.

Testing of asynchronous designs by "inappropriate" means. Synchronous approach

Abstract: The roadblock to wide acceptance of asynchronous methodology is poor CAD support. Current asynchronous design tools require a significant re-education of designers, and their capabilities are far behind synchronous commercial tools. This paper considers the testing methodology for a particular subclass of asynchronous circuits (Null Convention Logic or NCL) that entirely relies on conventional CAD tools available at today's market. It is shown that for acyclic NCL pipelines a test pattern generation for stuck-at faults could be effectively solved through the construction and checking of the synchronous circuit with a set of faults "equivalent" to the original NCL circuit. This result is extended to arbitrary NCL structures by applying the partial scan technique to break computational loops. The method guarantees 100% stuck-at fault coverage in NCL systems, which is confirmed by experimental data.

A proof engine approach to solving combinational design automation problems

Abstract: There are many approaches available for solving combinational design automation problems encoded as tautology or satisfiability checks. Unfortunately there exists no single analysis that gives adequate performance for all problems of interest, and it is therefore critical to be able to combine approaches. In this paper, we present a proof engine framework where individual analyses are viewed as strategies-functions between different proof states. By defining our proof engine in such a way that we can compose strategies to form new, more powerful, strategies we achieve synergistic effects between the individual methods. The resulting framework has enabled us to develop a small set of powerful composite default strategies. We describe several strategies and their interplay; one of the strategies, variable instantiation, is new. The strength of our approach is demonstrated with experimental results showing that our default strategies can achieve up to several magnitudes of speed-up compared to BDD-based techniques and search-based satisfiability solvers such as ZCHAFF.

The art and science of integrated systems design

Abstract: The design of next-generation integrated systems requires that "Art", a mix of knowledge, experience, intuition and creativeness, be supported by "Science", i.e., design methodologies that provide rigorous foundations and guarantee correctness either by construction or by a set of powerful synthesis and verification tools. We present platform-based design as the overarching principle to develop a class of methodologies that satisfy in part the requirements set above. A platform is an abstraction layer that hides the details of several possible implementation refinements of the underlying layers. We discuss the importance of carefully defining the platform layers and formally deriving the transitions from one platform to the next, including the role of top-down constraint propagation and bottom-up performance estimation. Finally, we present examples of these concepts at different key articulation points of the design process: system platforms and implementation platforms including analog design, thus covering the entire spectrum of design from conception and algorithms to final SoC implementation.

Constructive tool design for formal languages : from semantics to executing models

Abstract: Embedded, distributed, real-time, electronic systems are becoming more and more dominant in our lives. Hidden in cars, televisions, mp3-players, mobile phones and other appliances, these hardware/software systems influence our daily activities. Their design can be a huge effort and has to be carried out by engineers in a limited amount of time. Computer-aided modelling and design automation shorten the design cycle of these systems enabling companies to deliver their products sooner than their competitors. The design process is divided into different levels of abstraction, starting with a vague product idea (abstract) and ending up with a concrete description ready for implementation. Recently, research has started to focus on the system level, being a promising new area at which the product design could start. This dissertation develops a constructive approach to building tools for system-level design/description/modelling/specification languages, and shows the applicability of this method to the system-level language POOSL (Parallel Object-Oriented Specification Language). The formal semantics of this language is redefined and partly redeveloped, adding probabilistic features, real-time, inheritance, concurrency within processes, dynamic ports and atomic (indivisible) expressions, making the language suitable for performance analysis/modelling. The semantics is two-layered, using a probabilistic denotational semantics for stating the meaning of POOSL’s data layer, and using a probabilistic structural operational semantics for the process layer and architecture layer. The constructive approach has yielded the system-level simulation tool rotalumis, capable of executing large industrial designs, which has been demonstrated by two successful case studies—an ATM-packet switch (in conjunction with IBM Research at Z¨urich) and a packet routing switch for the Internet (in association with Alcatel/Bell at Antwerp). The more generally applicable optimisations of the execution engine (rotalumis) and the decisions taken in its design are discussed in full detail. Prototyping, where the system-level model functions as a part of the prototype implementation of the designed product, is supported by rotalumis-rt, a real-time variant of the execution engine. The viability of prototyping is shown by a case study of a learning infrared remote control, partially realised in hardware and completed with a system-level model. Keywords formal languages / formal specification / modelling languages / systemlevel design / embedded systems / real-time systems / performance analysis / discrete event simulation / probabilistic process algebra / design automation / prototyping / simulation tool.