Showing papers on "Electronic design automation published in 2014"

Challenges and Opportunities for Design, Simulation, and Fabrication of Soft Robots

Abstract: This article describes new opportunities in soft robotics and some potential avenues to overcome challenges associated with the realization of these opportunities. New opportunities include new applications that exploit novel amorphous nonrigid dynamics, a new design space due to the elimination of traditional manufacturing constraints, more opportunities for modeling and mimicry of natural systems, and increased safety and mechanical compatibility with humans. Challenges include limited simulation and design automation tools, lack of soft actuation methods, and difficulty in manufacturing and component standardization. Both computational (e.g., evolutionary design tools) and mechanical (porous and jamming materials) approaches are proposed to alleviate these needs.

A Contract-Based Methodology for Aircraft Electric Power System Design

Abstract: In an aircraft electric power system, one or more supervisory control units actuate a set of electromechanical switches to dynamically distribute power from generators to loads, while satisfying safety, reliability, and real-time performance requirements. To reduce expensive redesign steps, this control problem is generally addressed by minor incremental changes on top of consolidated solutions. A more systematic approach is hindered by a lack of rigorous design methodologies that allow estimating the impact of earlier design decisions on the final implementation. To achieve an optimal implementation that satisfies a set of requirements, we propose a platform-based methodology for electric power system design, which enables independent implementation of system topology (i.e., interconnection among elements) and control protocol by using a compositional approach. In our flow, design space exploration is carried out as a sequence of refinement steps from the initial specification toward a final implementation by mapping higher level behavioral and performance models into a set of either existing or virtual library components at the lower level of abstraction. Specifications are first expressed using the formalisms of linear temporal logic, signal temporal logic, and arithmetic constraints on Boolean variables. To reason about different requirements, we use specialized analysis and synthesis frameworks and formulate assume guarantee contracts at the articulation points in the design flow. We show the effectiveness of our approach on a proof-of-concept electric power system design.

Reverse Engineering Digital Circuits Using Structural and Functional Analyses

Abstract: Integrated circuits (ICs) are now designed and fabricated in a globalized multivendor environment making them vulnerable to malicious design changes, the insertion of hardware Trojans/malware, and intellectual property (IP) theft. Algorithmic reverse engineering of digital circuits can mitigate these concerns by enabling analysts to detect malicious hardware, verify the integrity of ICs, and detect IP violations. In this paper, we present a set of algorithms for the reverse engineering of digital circuits starting from an unstructured netlist and resulting in a high-level netlist with components such as register files, counters, adders, and subtractors. Our techniques require no manual intervention and experiments show that they determine the functionality of ${>}{45\%}$ and up to 93% of the gates in each of the test circuits that we examine. We also demonstrate that our algorithms are scalable to real designs by experimenting with a very large, highly-optimized system-on-chip (SOC) design with over 375000 combinational elements. Our inference algorithms cover 68% of the gates in this SOC. We also demonstrate that our algorithms are effective in aiding a human analyst to detect hardware Trojans in an unstructured netlist.

Circuit Camouflage Integration for Hardware IP Protection

Abstract: Circuit camouflage technologies can be integrated into standard logic cell developments using traditional CAD tools. Camouflaged logic cells are integrated into a typical design flow using standard front end and back end models. Camouflaged logic cells obfuscate a circuit's function by introducing subtle cell design changes at the GDS level. The logic function of a camouflaged logic cell is extremely difficult to determine through silicon imaging analysis preventing netlist extraction, clones and counterfeits. The application of circuit camouflage as part of a customer's design flow can protect hardware IP from reverse engineering. Camouflage fill techniques further inhibit Trojan circuit insertion by completely filling the design with realistic circuitry that does not affect the primary design function. All unused silicon appears to be functional circuitry, so an attacker cannot find space to insert a Trojan circuit. The integration of circuit camouflage techniques is compatible with standard chip design flows and EDA tools, and ICs using such techniques have been successfully employed in high-attack commercial and government segments. Protected under issued and pending patents.

Regaining Trust in VLSI Design: Design-for-Trust Techniques

Abstract: Designers use third-party intellectual property (IP) cores and outsource various steps in their integrated circuit (IC) design flow, including fabrication. As a result, security vulnerabilities have been emerging, forcing IC designers and end-users to reevaluate their trust in hardware. If an attacker gets hold of an unprotected design, attacks such as reverse engineering, insertion of malicious circuits, and IP piracy are possible. In this paper, we shed light on the vulnerabilities in very large scale integration (VLSI) design and fabrication flow, and survey design-for-trust (DfTr) techniques that aim at regaining trust in IC design. We elaborate on four DfTr techniques: logic encryption, split manufacturing, IC camouflaging, and Trojan activation. These techniques have been developed by reusing VLSI test principles.

OpenMETA: A Model- and Component-Based Design Tool Chain for Cyber-Physical Systems

Abstract: Model- and component-based design have yielded dramatic increase in design productivity in several narrowly focused homogeneous domains, such as signal processing, control and aspects of electronic design. However, significant impact on the design and manufacturing of complex cyber-physical systems (CPS) such as vehicles has not yet been achieved. This paper describes challenges of and solution approaches to building a comprehensive design tool suite for complex CPS. The primary driver for the OpenMETA tool chain was to push the boundaries of the “correct-by-construction” principle to decrease significantly the costly design-build-test-redesign cycles in design flows. In the discussions we will focus on the impact of heterogeneity in modeling CPS. This challenge is compounded by the need for rapidly evolving the design flow by changing/updating the selection of modeling languages, analysis and verification tools and synthesis methods. Based on our experience with the development of OpenMETA and with the evaluation of its performance in a complex CPS design challenge we argue that the current vertically integrated, discipline-specific tool chains for CPS design need to be complemented with horizontal integration layers that support model integration, tool integration and design process integration. This paper will examine the OpenMETA technical approach to construct the new integration layers, provides and overview of the technical framework we established for their implementation and summarize our experience with their application.

An LDPC Decoder With Time-Domain Analog and Digital Mixed-Signal Processing

Abstract: Time-domain analog and digital mixed-signal processing (TD-AMS) is presented. Analog computation is more energy- and area-efficient at the cost of its limited accuracy, whereas digital computation is more versatile and derives greater benefits from technology scaling. Besides, design automation tools for digital circuits are much more sophisticated than those for analog circuits. TD-AMS exploits both advantages, and is a solution better suited to implementing a system on chip including functions for which high computational accuracy is not required, such as error correction, image processing, and machine learning. As an example, a low-density parity-check (LDPC) code decoder with the technique is implemented in 65 nm CMOS and achieves the best reported efficiencies of 10.4 pJ/bit and 6.1 Gbps/mm2.

Advanced Field-Solver Techniques for RC Extraction of Integrated Circuits

Abstract: Resistance and capacitance (RC) extraction is an essential step in modeling the interconnection wires and substrate coupling effect in nanometer-technology integrated circuits (IC). The field-solver techniques for RC extraction guarantee the accuracy of modeling, and are becoming increasingly important in meeting the demand for accurate modeling and simulation of VLSI designs. Advanced Field-Solver Techniques for RC Extraction of Integrated Circuits presents a systematic introduction to, and treatment of, the key field-solver methods for RC extraction of VLSI interconnects and substrate coupling in mixed-signal ICs. Various field-solver techniques are explained in detail, with real-world examples to illustrate the advantages and disadvantages of each algorithm.This book will benefit graduate students and researchers in the field of electrical and computer engineering as well as engineers working in the IC design and design automation industries.Dr. Wenjian Yu is an Associate Professor at the Department of Computer Science and Technology at Tsinghua University in China; Dr. Xiren Wang is a R&D Engineer at Cadence Design Systems in the USA.

Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating

Abstract: Clock gating is a predominant technique used for power saving. It is observed that the commonly used synthesis-based gating still leaves a large amount of redundant clock pulses. Data-driven gating aims to disable these. To reduce the hardware overhead involved, flip-flops (FFs) are grouped so that they share a common clock enabling signal. The question of what is the group size maximizing the power savings is answered in a previous paper. Here we answer the question of which FFs should be placed in a group to maximize the power reduction. We propose a practical solution based on the toggling activity correlations of FFs and their physical position proximity constraints in the layout. Our data-driven clock gating is integrated into an Electronic Design Automation (EDA) commercial backend design flow, achieving total power reduction of 15%-20% for various types of large-scale state-of-the-art industrial and academic designs in 40 and 65 manometer process technologies. These savings are achieved on top of the sClock gating is a predominant technique used for power saving. It is observed that the commonly used synthesis-based gating still leaves a large amount of redundant clock pulses. Data-driven gating aims to disable these. To reduce the hardware overhead involved, flip-flops (FFs) are grouped so that they share a common clock enabling signal. The question of what is the group size maximizing the power savings is answered in a previous paper. Here we answer the question of which FFs should be placed in a group to maximize the power reduction. We propose a practical solution based on the toggling activity correlations of FFs and their physical position proximity constraints in the layout. Our data-driven clock gating is integrated into an Electronic Design Automation (EDA) commercial backend design flow, achieving total power reduction of 15%-20% for various types of large-scale state-of-the-art industrial and academic designs in 40 and 65 manometer process technologies. These savings are achieved on top of the savings obtained by clock gating synthesis performed by commercial EDA tools, and gating manually inserted into the register transfer level design.avings obtained by clock gating synthesis performed by commercial EDA tools, and gating manually inserted into the register transfer level design.

A GPU-Accelerated Web-Based Synthesis Tool for CT Sigma-Delta Modulators

Abstract: This paper presents a design environment for continuous-time sigma-delta analog-to-digital converters for automatic coefficient scaling using a genetic algorithm. In order to provide an interactive design tool which enables the designer to transform and refine basic performance specifications into the desired, detailed high-level filter description, a short response time is mandatory. Previously published heuristic-search-based design tools have response times in the range of several ten minutes up to hours and are mostly not freely available. In contrast, the design environment presented in this paper provides results in less than a minute due the utilization of a fast simulation method implemented on a graphics card processor. Our hardware supported approach allows performing between 10 k and 67 k simulations and evaluations per second for internal model orders of one to eight, allowing to investigate millions of settings in less than a minute.

Design methodologies for silicon photonic integrated circuits

Abstract: This paper describes design methodologies developed for silicon photonics integrated circuits. The approach presented is inspired by methods employed in the Electronics Design Automation (EDA) community. This is complemented by well established photonic component design tools, compact model synthesis, and optical circuit modelling. A generic silicon photonics design kit, as described here, is available for download at http://www.siepic.ubc.ca/GSiP.

IOPT-tools — Towards cloud design automation of digital controllers with Petri nets

Abstract: This paper describes the IOPT-Tools cloud-based tool-chain, offering a complete set of Petri net tools with a Web interface supporting digital controllers development. The tools include an interactive graphical Petri net editor, a model-checking subsystem composed of a state-space generator, state-space visualization and a query system, and automatic code generation tools that produce software “C” code or VHDL hardware descriptions ready to be deployed into implementation platforms. All interactive tools are executed directly in the user's Web Browser using AJAX principles, but file-storage and intensive processing operations are processed in the cloud. For example, state-space computation and the storage of the resulting data is performed in dedicated fast servers, minimizing network traffic and enabling the use of lightweight terminal equipment to access the tools, as simple as smart-phones or tablet computers. The tools are available on-line at http://gres.uninova.pt.

Combining aspects and object-orientation in model-driven engineering for distributed industrial mechatronics systems

Abstract: Recent advances in technology enable the creation of complex industrial systems comprising mechanical, electrical, and logical – software – components. It is clear that new project techniques are demanded to support the design of such systems. At design phase, it is extremely important to raise abstraction level in earlier stages of product development in order to deal with such a complexity in an efficient way. This paper discusses Model Driven Engineering (MDE) applied to design industrial mechatronics systems. An aspect-oriented MDE approach is presented by means of a real-world case study, comprising requirements engineering up to code generation. An assessment of two well-known high-level paradigms, namely Aspect- and Object-Oriented paradigms, is deeply presented. Their concepts are applied at every design step of an embedded and real-time mechatronics system, specifically for controlling a product assembler industrial cell. The handling of functional and non-functional requirements (at modeling level) using aspects and objects is further emphasized. Both designs are compared using a set of software engineering metrics, which were adapted to be applied at modeling level. Particularly, the achieved results show the suitability of each paradigm for the system specification in terms of reusability quality of model elements. Focused on the generated code for each case study, statistics depicted an improvement in number of lines using aspects.

Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits

Abstract: Design automation techniques are a key challenge in the widespread application of timing-robust asynchronous circuit styles. In this paper, a new methodology for mapping multi-rail logic expressions to a NULL convention logic (NCL) gate library is proposed. The new methodology is then compared to another recently proposed mapping approach, demonstrating that the new methodology can further reduce the area and improve the delay of NCL circuits. Also, in contrast to the original approach, which only targets area reduction, the new methodology can target any arbitrary cost function or use any subset of the NCL gate library for mapping. In order to automate the new methodology and compare it with the original one, both methodologies were implemented in the Perl programming language and compared in terms of mapping performance and runtime. The results show that, depending on the test circuit, the new methodology can offer up to 10% improvement in area, and 39% improvement in delay.

Rapid Post-Map Insertion of Embedded Logic Analyzers for Xilinx FPGAs

Abstract: A rapid post-map insertion of an embedded logic analyzer is discussed. The proposed technique makes use of otherwise unused resources in an already-mapped circuit and does not disturb the original placement and routing of the circuit. Using this technique, designers can add debugging circuitry to existing circuits and quickly modify the set of observed signals in just a few minutes instead of waiting for a recompile of their circuit. All tests were performed on a Xilinx Virtex-5 FPGA.

A defect-based compact modeling approach for the reliability of CMOS devices and integrated circuits

Abstract: Reliability simulations are critical for lifetime prediction and verification of long-term performance of integrated circuits designed in advanced CMOS technologies. The existing techniques for reliability simulation model aging effects using threshold voltage ( V th ) shifts that do not reflect the bias-dependence of stress-induced defects. In this work we present a defect-based modeling approach that captures the dynamic effects of both oxide-trapped charge and interface traps through calculations of surface potential. Such defects are attributed to aging effects and to ionizing–radiation damage in advanced CMOS technologies. The approach provides a connection between physics-based reliability models and integrated circuit simulation. The model is implemented as a Verilog-A sub-circuit module and is compatible with standard EDA tools and MOSFET compact models. The model formulation is verified using two-dimensional TCAD simulations. Demonstrations with digital integrated circuit simulations in SPICE and comparisons with calculations using V th -based models are also presented.

Modeling Biology With HDL Languages: A First Step Toward a Genetic Design Automation Tool Inspired From Microelectronics

Abstract: Nowadays, synthetic biology is a hot research topic. Each day, progresses are made to improve the complexity of artificial biological functions in order to tend to complex biodevices and biosystems. Up to now, these systems are handmade by bioengineers, which require strong technical skills and leads to nonreusable development. Besides, scientific fields that share the same design approach, such as microelectronics, have already overcome several issues and designers succeed in building extremely complex systems with many evolved functions. On the other hand, in systems engineering and more specifically in microelectronics, the development of the domain has been promoted by both the improvement of technological processes and electronic design automation tools. The work presented in this paper paves the way for the adaptation of microelectronics design tools to synthetic biology. Considering the similarities and differences between the synthetic biology and microelectronics, the milestones of this adaptation are described. The first one concerns the modeling of biological mechanisms. To do so, a new formalism is proposed, based on an extension of the generalized Kirchhoff laws to biology. This way, a description of all biological mechanisms can be made with languages widely used in microelectronics. Our approach is therefore successfully validated on specific examples drawn from the literature.

A complete design flow for silicon photonics

Abstract: Broad adoption of silicon photonics technology for photonic integrated circuits requires standardized design flows that are similar to what is available for analog and mixed signal electrical circuit design. We have developed a design flow that combines mature electronic design automation (EDA) software with optical simulation software. An essential component of any design flow, whether electrical or photonic, is the ability to accurately simulate largescale circuits. This is particularly important when the behavior of the circuit is not trivially related to the individual component performance. While this is clearly the case for electronic circuits consisting of hundreds to billions of transistors, it is already becoming important in photonic circuits such as WDM transmitters, where signal cross talk needs to be considered, as well as optical cross-connect switches. In addition, optical routing to connect different components requires the introduction of additional waveguide sections, waveguide bends, and waveguide crossings, which affect the overall circuit performance. Manufacturing variability can also have dramatic circuit-level consequences that need to be simulated. Circuit simulations must rely on compact models that can accurately represent the behavior of each component, and the compact model parameters must be extracted from physical level simulation and experimental results. We show how large scale circuits can be simulated in both the time and frequency domains, including the effects of bidirectional and, where appropriate, multimode and multichannel photonic waveguides. We also show how active, passive and nonlinear individual components such as grating couplers, waveguides, splitters, filters, electro-optical modulators and detectors can be simulated using a combination of electrical and optical algorithms, and good agreement with experimental results can be obtained. We then show how parameters, with inclusion of fabrication process variations, can be extracted for use in the circuit level simulations. Ultimately, we show how a multi-channel WDM transceiver can be created, from schematic design to tapeout, using key features of EDA design flows such as schematic driven layout, design rule checking and layout versus schematic.

Moving from co-simulation to simulation for effective smart systems design

Abstract: Design of smart systems needs to cover a wide variety of domains, ranging from analogue to digital, with power devices, micro-sensors and actuators, up to MEMS. This high level of heterogeneity makes design a very challenging task, as each domain is supported by specific languages, modeling formalisms and simulation frameworks. A major issue is furthermore posed by simulation, that heavily impacts the design and verification loop and that is very hard to be built in such an heterogeneous context. On the other hand, achieving efficient simulation would indeed make smart system design feasible with respect to budget constraints. This work provides a formalization of the typical abstraction levels and design domains of a smart system. This taxonomy allows to identify a precise role in the design flow for co-simulation and simulation scenarios. Moreover, a methodology is proposed to move from the co-simulated heterogeneity to a simulatable homogeneous representation in C++ of the entire smart system. The impact of heterogeneous or homogeneous models of computation is also examined. Experimental results prove the effectiveness of the proposed C++ generation for reaching high-speed simulation.

Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?

Abstract: Quasi delay-insensitive design is a promising solution for coping with contemporary silicon technology problems such as aggressive process variations and tight power budgets. However, one major barrier to its wider adoption is the lack of automated optimization techniques for building circuits using semi-custom methodologies. This paper proposes an innovative design flow that relies on the use of consolidated commercial EDA frameworks for synthesizing 1-of-n 4-phase quasi delay-insensitive circuits using Null Convention Logic. Asynchronous gates that are usually not supported by these frameworks are modelled as conventional logic gates, allowing synthesis tools to perform static timing analysis as well as pre- and post-mapped design optimizations, which can be specified by the designer using conventional timing constraints.

A Top-Down Constraint-Driven Methodology for Smart System Design

Abstract: Smart Systems collate leading technologies and solutions for the design of new generation embedded and cyber-physical systems. They can be applied to a broad range of application domains, from everyday life to mission and safety critical tasks, and achieve a wide set of functionality using diverging architectures. Smart system design needs to be achieved in a real multi-domain environment, where analog, digital, mixed-signal, and now even MEMS sub-systems tightly interact. With a traditional approach, these different units are designed separately, and finally merged at the electronic system level. However, given the increasing integration and interactions among components of different nature, methodologies enabling effective system-level architectural exploration are becoming more and more significant. Starting from a detailed analysis and classification of state-of-the-art use scenarios, and based on a review of the existing approaches, we present a top-down constraint-driven methodology for the design of new generation smart systems. It enables partitioning and propagation of high-level application-driven requisites towards low-level units in the design flow. The methodology reviews fundamental and cross-sectional system-level design aspects applied to the definition of an example case, to identify sub-system requirements towards the specifications of the electrical features of each internal unit.

Editorial: ACM Transactions on Design Automation of Electronics Systems and Beyond

Abstract: For more than fifty years, research in Electronic Design Automation (EDA) has evolved from physical design and logic synthesis to the entire system design framework, including system-on-chip architectures, hardware/software codesign, verification, testing, power/thermal management, design for manufacturability, analog design, security, and even embedded systems/software design/design methodologies. Since the beginning, advancement in semiconductor scaling has been heavily dependent on EDA. Without EDA, semiconductor scaling would not be possible despite dramatic growth in physics, material sciences, and device technologies. Recently, EDA research has been rapidly expanding its application areas to a wide-range of vertical integrations such as biomedical applications, energy systems, data centers, electromobility, cyber-physical systems, Internet of Things, hardware security, mobile applications, etc. ACM Transactions on Design Automation of Electronic Systems (TODAES) has been publishing recent significant results of research and development efforts in the area of design automation of electronic systems. The TODAES editorial board invites submission of technical articles describing these results. The journal intends to provide a comprehensive coverage of innovative work concerning the specification, design, analysis, simulation, testing, and evaluation of very large scale integrated electronic systems, emphasizing a computer science/engineering orientation. Meanwhile, EDA must fulfill the expectations of designers through more efficient cross-layer tighter integration from devices to software. The EDA community has the responsibility to take on these challenges because EDA has been in the forefront of developing optimal (or near-optimal) systematic, scalable solution methods compared with other domains. In the coming years, EDA will no longer be electronics design automation but smart planet design automation. This is an exciting time for ACM TODAES and beyond. ACM TODAES should reach out for these new opportunities during the next decade. ACM TODAES now gives strong emphasis on Design Automation of Things, including new/emerging device technologies and CAD applications and design automation of bio, energy, and cyber-physical systems, design methodologies and design automation technologies for security of hardware and embedded systems. However, simply publishing new domain research articles must not be the sole goal of ACM TODAES. Rather, ACM TODAES should lead the direction of EDA so that larger and more complex new domain problems are formulated and systematically solved by EDA-context design methodologies and design automation. The ACM TODAES Editorial Board knows that steadfast administration is the key to successfully building and maintaining the highest standard and reputation for the journal. ACM TODAES will strive to make the time-to-first-decision for submitted

j5 DNA Assembly Design Automation

Abstract: Modern standardized methodologies, described in detail in the previous chapters of this book, have enabled the software-automated design of optimized DNA construction protocols. This chapter describes how to design (combinatorial) scar-less DNA assembly protocols using the web-based software j5. j5 assists biomedical and biotechnological researchers construct DNA by automating the design of optimized protocols for flanking homology sequence as well as type IIS endonuclease-mediated DNA assembly methodologies. Unlike any other software tool available today, j5 designs scar-less combinatorial DNA assembly protocols, performs a cost-benefit analysis to identify which portions of an assembly process would be less expensive to outsource to a DNA synthesis service provider, and designs hierarchical DNA assembly strategies to mitigate anticipated poor assembly junction sequence performance. Software integrated with j5 add significant value to the j5 design process through graphical user-interface enhancement and downstream liquid-handling robotic laboratory automation.

Data Mining In EDA - Basic Principles, Promises, and Constraints

Abstract: This paper discusses the basic principles of applying data mining in Electronic Design Automation. It begins by introducing several important concepts in statistical learning and summarizes different types of learning algorithms. Then, the experience of developing a practical data mining application is described, including promises that are demonstrated through positive results based on industrial settings and constraints explained in their respective application contexts.

A 72-Port 10G Ethernet Switch/Router Using Quasi-Delay-Insensitive Asynchronous Design

Abstract: The design of a commercially-shipping 72-port 10G Ethernet switch router integrated circuit is presented. The 1.2 billion transistor chip consists of a core of > 1GHz asynchronous circuits surrounded by standard synchronous logic for external interfaces. It is manufactured in a TSMC 65nm process. The asynchronous circuitry includes 15MB of single-ported SRAM, 150KB of dual-ported SRAM, 100KB of TCAM, Tb bandwidth crossbars, and a fully pipelined programmable packet processor processing one billion packets per second. The design implementation relied heavily on a novel tool flow utilizing both commercial and proprietary EDA tools for automatic place-and-route of asynchronous layout.

Synthesis of Processor Instruction Sets from High-Level ISA Specifications

Abstract: As processors continue to get exponentially cheaper for end users following Moore’s law, the costs involved in their design keep growing, also at an exponential rate. The reason is ever increasing complexity of processors, which modern EDA tools struggle to keep up with. This paper focuses on the design of Instruction Set Architecture (ISA), a significant part of the whole processor design flow. Optimal design of an instruction set for a particular combination of available hardware resources and software requirements is crucial for building processors with high performance and energy efficiency, and is a challenging task involving a lot of heuristics and high-level design decisions. This paper presents a new compositional approach to formal specification and synthesis of ISAs. The approach is based on a new formalism, called Conditional Partial Order Graphs, capable of capturing common behavioural patterns shared by processor instructions, and therefore providing a very compact and efficient way to represent and manipulate ISAs. The Event-B modelling framework is used as a formal specification and verification back-end to guarantee correctness of ISA specifications. We demonstrate benefits of the presented methodology on several examples, including Intel 8051 microcontroller.

Advanced Symbolic Analysis for VLSI Systems: Methods and Applications

Abstract: This book provides comprehensive coverage of the recent advances in symbolic analysis techniques for design automation of nanometer VLSI systems. The presentation is organized in parts of fundamentals, basic implementation methods and applications for VLSI design. Topics emphasized includestatistical timing and crosstalk analysis, statistical and parallel analysis, performance bound analysis and behavioral modeling for analog integrated circuits. Among the recent advances, the Binary Decision Diagram (BDD) based approaches are studied in depth. The BDD-based hierarchical symbolic analysis approaches, have essentially broken the analog circuit size barrier.

Multi-disciplinary integrated design automation tool for automotive cyber-physical systems

Abstract: This paper presents our multi-year experience in the development of a Functional Modeling Compiler (FMC), a new model-based design tool for the development of multi-disciplinary automotive cyber-physical systems. We show how system-level simulation models suitable for design-space exploration of complex architectures can be synthesized from functional specifications to test and validate the interactions between ECUs, control algorithms, and the multi-physics.