Showing papers on "Field-effect transistor published in 1989"

The Monte Carlo Method for Semiconductor Device Simulation

Abstract: 1 Introduction.- References.- 2 Charge Transport in Semiconductors.- 2.1 Electron Dynamics.- 2.2 Energy Bands.- 2.2.1 Relationship of Energy to Wavevector.- 2.2.2 Effective Masses.- 2.2.3 Nonparabolicity.- 2.2.4 Herring and Vogt Transformation.- 2.2.5 Actual Bands of Real Semiconductors.- 2.3 Scattering Mechanisms.- 2.3.1 Classification and Physical Discussion.- 2.3.2 Fundamentals of Scattering.- 2.4 Scattering Probabilities.- 2.4.1 Phonon Scattering, Deformation-Potential Interaction.- 2.4.2 Phonon Scattering, Electrostatic Interaction.- 2.4.3 Ionized Impurity Scattering.- 2.4.4 Carrier-Carrier Scattering.- 2.5 Transport Equation.- 2.6 Linear Response and the Relaxation Time Approximation.- 2.6.1 Relaxation Times for the Various Scattering Mechanisms.- 2.6.2 Carrier Mobilities in Various Materials.- 2.7 Diffusion, Noise, and Velocity Autocorrelation Function.- 2.7.1 Basic Macroscopic Equations of Diffusion.- 2.7.2 Diffusion, Autocorrelation Function, and Noise.- 2.7.3 Electron Lifetime and Diffusion Length.- 2.8 Hot Electrons.- 2.9 Transient Transport.- 2.10 The Two-dimensional Electron Gas.- 2.10.1 Subband Levels and Wavefunctions.- 2.10.2 Scattering Rates.- References.- 3 The Monte Carlo Simulation.- 3.1 Fundamentals.- 3.2 Definition of the Physical System.- 3.3 Initial Conditions.- 3.4 The Free Flight, Self Scattering.- 3.5 The Scattering Process.- 3.6 The Choice of the State After Scattering.- 3.6.1 Phonon Scattering, Deformation-Potential Interaction.- 3.6.2 Phonon Scattering, Electrostatic Interaction.- 3.6.3 Ionized Impurity Scattering.- 3.6.4 Carrier-Carrier Scattering.- 3.7 Collection of Results for Steady-State Phenomena.- 3.7.1 Time Averages.- 3.7.2 Synchronous Ensemble.- 3.7.3 Statistical Uncertainty.- 3.8 The Ensemble Monte Carlo (EMC).- 3.9 Many Particle Effects.- 3.9.1 Carrier-Carrier Scattering.- 3.9.2 Molecular Dynamics and Monte Carlo Method.- 3.9.3 Degeneracy in Monte Carlo Calculations.- 3.10 Monte Carlo Simulation of the 2DEG.- 3.11 Special Topics.- 3.11.1 Periodic Fields.- 3.11.2 Diffusion, Autocorrelation Function, and Noise.- 3.11.3 Ohmic Mobility.- 3.11.4 Impact Ionization.- 3.11.5 Magnetic Fields.- 3.11.6 Optical Excitation.- 3.11.7 Quantum Mechanical Corrections.- 3.12 Variance-reducing Techniques.- 3.12.1 Variance Due to Thermal Fluctuations.- 3.12.2 Variance Due to Valley Repopulation.- 3.12.3 Variance Related to Improbable Electron States.- 3.13 Comparison with Other Techniques.- 3.13.1 Analytical Techniques.- 3.13.2 The Iterative Technique.- 3.13.3 Comparison of the Different Techniques.- References.- 4 Review of Semiconductor Devices.- 4.1 Introduction.- 4.2 Historical Evolution of Semiconductor Devices.- 4.2.1 Evolution of Si Devices.- 4.2.2 Evolution of GaAs Devices.- 4.2.3 Technological Features.- 4.2.4 Scaling and Miniaturization.- 4.3 Physical Basis of Semiconductor Devices.- 4.3.1 p-n Junction.- 4.3.2 Bipolar Transistors.- 4.3.3 Heterojunction Bipolar Transistor.- 4.3.4 Metal-Semiconductor Contacts.- 4.3.5 Metal-Semiconductor Field-Effect Transistor.- 4.3.6 Metal-Oxide-Semiconductor Field-Effect Transistor.- 4.3.7 High Electron Mobility Transistor.- 4.3.8 Hot Electron Transistors.- 4.3.9 Permeable Base Transistor.- 4.4 Comparison of Semiconductor Devices.- 4.4.1 Device Parameters.- 4.4.2 Comparison of Semiconductor Devices.- References.- 5 Monte Carlo Simulation of Semiconductor Devices.- 5.1 Introduction.- 5.2 Geometry of the System.- 5.2.1 Boundary Conditions.- 5.2.2 Grid Definition.- 5.2.3 Superparticles.- 5.3 Particle-Mesh Force Calculation.- 5.3.1 Particle-Mesh Calculation in One Dimension.- 5.3.2 Charge Assignment Schemes in Two Dimensions.- 5.4 Poisson Solver and Field Distribution.- 5.4.1 Finite Difference Scheme.- 5.4.2 Matrix Methods.- 5.4.3 Rapid Elliptic Solvers (RES).- 5.4.4 Iterative Methods.- 5.4.5 Calculation of the Electric Field.- 5.4.6 The Collocation Method.- 5.5 The Monte Carlo Simulation of Semiconductor Devices.- 5.5.1 Initial Conditions.- 5.5.2 Time Cycles.- 5.5.3 Free Flight.- 5.5.4 Scattering.- 5.5.5 Carrier-Carrier Scattering.- 5.5.6 Degenerate Statistics.- 5.5.7 Statistics.- 5.5.8 Static Characteristics.- 5.5.9 A.C. Characteristics.- 5.5.10 Noise.- References.- 6 Applications.- 6.1 Introduction.- 6.2 Diodes.- 6.2.1 n+-n-n+ Diodes.- 6.2.2 Schottky Diode.- 6.3 MESFET.- 6.3.1 Short Channel Effects.- 6.3.2 Geometry Effects.- 6.3.3 Space-Charge Injection FET.- 6.3.4 Conclusions.- 6.4 HEMT and Heterojunction Real Space Transfer Devices.- 6.4.1 HEMT.- 6.4.2 Real-Space Transfer Devices.- 6.4.3 Velocity-Modulation Field Effect Transistor.- 6.5 Bipolar Transistor.- 6.6 HBT.- 6.7 MOSFET and MISFET.- 6.7.1 MOSFET.- 6.7.2 GaAs Injection-modulated MISFET.- 6.7.3 Conclusions.- 6.8 Hot Electron Transistors.- 6.8.1 The THETA Device.- 6.8.2 GaAs FET with Hot-Electron Injection Structure.- 6.8.3 Planar-doped-Barrier Transistors.- 6.9 Permeable Base Transistor.- 6.10 Comparison with Traditional Simulators.- References.- Appendix A. Numerical Evaluation of Some Integrals of Interest.- References.- Appendix B. Generation of Random Numbers.- References.

Semiconductor Device Modeling with Spice

Abstract: From the Publisher: With all the clarity and hands-on practicality of the best-selling first edition,this revised version explains the ins and outs of SPICE,plus gives new data on modeling advanced devices such as MESFETs,ISFETs,and thyristors. And because it's the only book that describes the models themselves,it helps readers gain maximum value from SPICE,rather than just telling them how to run the program. This guide is also distinctive in covering both MOS and FET models. Step by step,it takes the reader through the modeling process,providing complete information on a variety of semiconductor devices for designing specific circuit applications. These include: Pn junction and Schottky diodes; bipolar junction transistor (BJT); junction field effect transistor (JFET); metal oxide semiconductor transistor (MOST); metal semiconductor field effect transistor (MESFET); ion sensitive field effect transistor (ISFET); semiconductor controlled rectifier (SCR-thyristor).

The physics of amorphous-silicon thin-film transistors

Abstract: The basic physics underlying the operation and key performance issues of amorphous-silicon thin-film transistors (TFTs) are discussed. The static transistor characteristics are determined by the localized electronic states that occur in the bandgap of the amorphous silicon. The deep states, mostly consisting of Si dangling bonds, determine the threshold voltage, and the conduction band-tail states determine the field-effect mobility. The finite capture and emission times of the deep localized states lead to a dynamic transistor characteristic that can be described by a time-dependent threshold voltage. The transistors also show longer time threshold voltage shifts due to two other distinct mechanisms: charge trapping in the silicon nitride gate insulator and metastable dangling bond state creation in the amorphous silicon. These two mechanisms show characteristically different bias, temperature, and time dependencies of the threshold voltage shift. Illumination of a TFT causes the generation of electron-hole pairs in the space-charge region leading to a steady-state equal flux of electrons and holes and a reduction in the band-bending. In most applications, the photosensitivity should be minimized. The uniformity of large arrays of transistors for display applications is excellent, with variations in the threshold voltage of 0.5-1.0 V. >

Analysis of the charge pumping technique and its application for the evaluation of MOSFET degradation

Abstract: It is shown that the charge pumping technique is able not only to determine the degradation mechanisms in MOS transistors under all kinds of aging conditions (eg, irradiation, hot-carrier, Fowler-Nordheim stress), but also in several cases to evaluate and to quantify the degradation It is further shown that the technique can be applied to separate the presence of fixed oxide changes due to charge trapping and the generation of interface traps It can be used to analyze degradations that occur uniformly over the transistor channel, as well as strongly localized transistor degradations (eg, for the case of hot-carrier degradations) All possible cases of uniform and nonuniform degradations, for p-channel as well as for n-channel transistors, are described, and for most of them experimental examples are given >

Theory for a quantum modulated transistor

Abstract: We present a theoretical study of semiconductor T‐structures which may exhibit transistor action based on quantum interference. The electron transmission through a semiconductor quantum wire can be controlled by an external gate voltage that modifies the penetration of the electron wavefunction in a lateral stub, affecting in this way its interference pattern. The structures are modeled as ideal two‐dimensional electron waveguides and a tight‐binding Green’s function technique is used to compute the electron transmission and reflection coefficients. The calculations show that relatively small changes in the stub length can induce strong variations in the electron transmission across the structure. Operation in the fundamental transverse mode appears to be important for applications. We also show that a bound state of purely geometrical origin nucleates at the intersection between waveguide and stub. The performance of the device can be improved by inserting additional stubs of slightly different lengths. ...

Short-channel effects in SOI MOSFETs

Abstract: Short-channel effects in thin-film silicon-on-insulator (SOI) MOSFETs are shown to be unique because of dependences on film thickness and body and back-gate (substrate) biases. These dependences enable control of threshold-voltage reduction, channel-charge enhancement due to a drain bias, carrier velocity saturation, channel-length modulation and its effect on output conductance, as well as device degradation due to hot carriers in short-channel SOI MOSFETs. A short-channel effect exclusive to SOI MOSFETs, back-surface charge modulation, is described. Because of the short-channel effects, the use of SOI MOSFETs in VLSI circuits provides the designer with additional flexibility as compared to bulk-MOSFET design. Various design tradeoffs are discussed. >

Method for forming a lightly-doped drain (LDD) structure in a semiconductor device

Abstract: A process is disclosed for the formation of an LDD structure in an MOS transistor having a reduced mask count and providing high integrity source/drain junctions. In accordance with one embodiment of the invention an MOS transistor is formed having a gate dielectric overlying an active region of the substrate. A transistor gate is formed in a central portion of the active region and an oxidation layer is formed over the active region and the transistor gate. A lightly-doped source/drain region is formed which is self aligned to the transistor gate. A conformal layer of an oxygen reactive material is formed overlying the transistor gate and the active region. The oxygen reactive material is anisotropically etched in a oxygen plasma reactive ion etch to form a sidewall spacer on the edge the transistor gate. The oxygen reactive ion etch does not penetrate the oxidation layer overlying the active region. A heavily-doped source/drain region is formed which is self aligned to the edge of the sidewall spacer. The sidewall spacer is then removed completing the LDD structure.

Split collector vacuum field effect transistor

Abstract: A vacuum FET is designed to perform higher level functions such as logic AND, EXCLUSIVE OR (NOR), demultiplexing, or frequency multiplication with a single device. These higher level functions are accomplished by dividing the collector of the vacuum FET into multiple segments and by providing steering electrodes just above the emitter to deflect the field emission current to the various collector segments. The collector pattern, together with the configuration of the applied signals to the device, determines the higher order function performed.

Two-dimensional simulation and measurement of high-performance MOSFETs made on a very thin SOI film

Abstract: Thinning effects on the device characteristics of silicon-on-insulator (SOI) MOSFETs are discussed. Two-dimensional/two-carrier device simulation revealed the following advantages. An n-channel MOSFET with 500-AA-SOI thickness exhibited a high-punchthrough resistance as well as an improved subthreshold swing down to a deep submicrometer region, even if the film was nearly intrinsic. A capacitance coupling model has been proposed to explain these subthreshold characteristics. The kink elimination effect, which was attributed to a significantly reduced hole density in the SOI film, was reproduced. The low-field channel mobility exhibited a significant increase, which was ascribed to a decrease in the vertical electric field. Moreover, the current-overshoot phenomenon associated with the switching operation was suppressed. Excess holes recombine with electrons quickly after the gate turn-on, bringing about a stabilized potential in the SOI substrate. Experiments were also carried out to verify the simulation. >

Characterization of front and back Si-SiO/sub 2/ interfaces in thick- and thin-film silicon-on-insulator MOS structures by the charge-pumping technique

Abstract: It is shown that the charge-pumping technique can be successfully applied to SOI structures, directly providing important and reliable information about the quality of both front- and back-gate interfaces. The possibility of performing measurements on a transistor level makes direct correlation with other MOS characteristics and material parameters possible. In particular, the ability of this technique to perform measurements on thin-film transistors and to separate the information from front and back gates makes it indispensable for characterization of advanced SOI CMOS structures. Although the technique was demonstrated only on 5- mu m channel length devices, it has sufficient sensitivity to be applicable to transistors of micrometer and submicrometer dimensions. Charge-pumping measurements on laser-recrystallized SOI MOSFETs showed that the front interface is only slightly deteriorated compared to that of bulk MOSFET devices, while the back interface is of a substantially lower quality, with about 10 times higher interface trap densities. >

Monolithic FET structures for high-power control component applications

Abstract: A monolithic FET switch is described that can be integrated with other monolithic functions or used as a discrete component in a microwave integrated circuit structure. This device increases the power-handling capability of the conventional single FET switch by an order of magnitude. It does this by overcoming the breakdown voltage limitation of the FET device. The design, fabrication and performance of two high-power control components using these circuits are described as examples of the implementation of this technology. They are an L-band terminated single-pole, single-throw (SPST) switch and an L-band limiter. >

A new asymmetrical halo source GOLD drain (HS-GOLD) deep sub-half-micrometer n-MOSFET design for reliability and performance

Abstract: A novel asymmetrical n-MOSFET device structure has been developed which is suitable, in terms of reliability and performance, for scaling down to the sub-quarter-micron level, without reduction of the supply voltage below 3.5 V. In this structure (HS-GOLD), large-tilt implantation is used to form the gate-overlapped lightly doped drain (GOLD) region at the drain electrode only. A halo (punch-through stopper) is used at the source, but not at the drain. Superior hot-carrier reliability and high punch-through resistance are obtained using this device structure. A reliability-limited supply voltage at 4.2 V is obtained for HS-GOLD n-MOSFETs with effective channel lengths as short as 0.25 mu m. High punch-through resistance is achieved without extreme scaling of S-D (source-drain) junctions and gate oxide (120 AA). The threshold roll-off characteristics suggest that this n-MOSFET structure can be designed with about 0.3 mu m shorter channel length (L/sub eff/=0.15 mu m) while maintaining the 3.5-V supply voltage. Reliable operation of 0.15- mu m n-MOSFETs at 3.5-V supply voltage using the proposed device structure is demonstrated by 2D simulation. >

Implanted silicon JFET on completely depleted high-resistivity devices

Abstract: To satisfy the increasing interest in the integration of electronics onto optical and ionizing particle fully depleted detectors, a nonconventional JFET (junction field-effect transistor), designed to operate on a completely depleted, 2-k Omega -cm resistivity silicon substrate, has been designed, fabricated, and tested at room temperature. The devices show very low gate leakage current, low output conductance, a transconductance per unit gate width of 3 mS/mm, and a pinch-off voltage of -1.5 V. The integration of the devices onto the detectors makes possible the matching of the input capacitance of the JFET to the detector's output capacitance, which is of the order of few hundreds of femtorads. The measured gate capacitance of 200 fF is shown to correspond to an expected resolution in charge measurements, at room temperature, of less than 40 electrons rms. The fabrication constraints, imposed by the limited number of production steps of the detectors, are reported. >

Field-Effect Transistors using Boron-Doped Diamond Epitaxial Films

Abstract: Metal-semiconductor field-effect transistors (MESFET's) have been fabricated on a boron-doped diamond epitaxial film. This is the first report of a planar type transistor using a diamond film.

Fabrication of detectors and transistors on high-resistivity silicon

Abstract: A new process for the fabrication of silicon p-i-n diode radiation detectors is described. The utilization of backside gettering in the fabrication process results in the actual physical removal of detrimental impurities from critical device regions. This reduces the sensitivity of detector properties to processing variables while yielding low diode reverse-leakage currents. In addition, gettering permits the use of processing temperatures compatible with integrated-circuit fabrication. P-channel MOSFETs and silicon p-i-n diodes have been fabricated simultaneously on 10 k..cap omega../center dot/cm silicon using conventional integrated-circuit processing techniques. 25 refs., 5 figs.

Fermi threshold field effect transistor

Abstract: A field effect transistor (FET) operates in the enhancement mode without requiring inversion by setting the device's threshold voltage to twice the Fermi potential of the semiconductor material. The FET, referred to as a Fermi Threshold FET or Fermi-FET, has a threshold voltage which is independent of oxide thickness, channel length, drain voltage and substrate doping, the vertical electric field in the channel becomes zero, thereby maximizing carrier mobility, and minimizing hot electron effects. A high speed device, substantially independent of device dimensions is thereby provided, which may be manufactured using relaxed groundrules, to provide low cost, high yield devices. Temperature dependence of threshold voltage may also be eliminated by providing a semiconductor gate contact which neutralizes the effect of substrate contact potential. Source and drain subdiffusion regions may be provided to simultaneously maximize the punch-through and impact ionization voltages of the devices, so that short channel devices do not require scaled-down power supply voltages. Multi gate devices may be provided. An accelerator gate, adjacent the drain, may further improve performance. The Fermi-FET criteria may be maintained, while allowing for a deep channel by providing a substrate contact for the Fermi-FET and applying a substrate bias to this contact. Substrate enhancement pocket regions adjacent the source and drain regions may be provided to produce a continuous depletion region under the source, drain and channel regions to thereby minimize punch-through effects.

CMOS digital level shifter circuit

Abstract: The apparatus of the present invention is a CMOS digital level shifter circuit which includes an inverter connected to a voltage generator. The voltage generator comprises an NMOS source follower connected to a directional switching element and a voltage regulating capacitor. The level shifter further includes a latch energized by the same voltage supply energizing the voltage generator. Each branch of the latch has a complementary MOS transistor pair with common gates connected to the output of the inverter and to the input signal respectively. Each complementary transistor pair is connected to the voltage supply by a latch transistor whose gate is cross-connected to the complementary transistor pair of the other branch. Whenever the one transistor in each complementary pair which is connected to ground is on, the latch transistor is latched off by the complementary transistor pair in the other branch after each voltage transition by the input signal, thereby reducing or eliminating DC power consumption, while requiring only a single voltage supply.

Lateral conductivity modulated MOSFET

Abstract: A conductivity modulated MOSFET, having a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the semiconductor substrate and having a high resistance, a base layer of the first conductivity type formed in the semiconductor layer, a source layer of the second conductivity type formed in the base layer, a gate electrode formed on a gate insulating film which is formed on a channel region, the channel region being formed in a surface of the base layer between the semiconductor layer and the source layer, a source electrode ohmic-contacting the source layer and the base layer, and a drain electrode formed on the surface of the semiconductor substrate opposite to the semiconductor layer, characterized in that the conductivity modulated MOSFET has a saturation current smaller than a latch-up current when a predetermined gate voltage is applied to the gate electrode.

Negative transconductance and negative differential resistance in a grid‐gate modulation‐doped field‐effect transistor

Abstract: We report on transport measurements in grid‐gate lateral‐surface‐superlattice (LSSL) field‐effect transistors on a modulation‐doped GaAs/AlGaAs heterostructure. The LSSL is created by a 0.2 μm period Ti/Au grid on top of the AlGaAs layer, which presents a tunable, two‐dimensional periodic potential modulation to the electrons traveling from source to drain. Current measurements at 4.2 K as a function of gate bias exhibit negative transconductance at a fixed drain bias below 15 mV, providing evidence of a superlattice effect (i.e., coherent back‐diffraction). In addition, negative differential resistance is observed at a fixed gate bias and a drain bias around 100 mV, which could be a manifestation of sequential resonant tunneling.

Reverse short-channel effects on threshold voltage in submicrometer salicide devices

Abstract: A reverse short-channel effect on threshold voltage caused by the self-aligned silicide process in submicrometer MOSFETs is reported. A physical model of lateral channel dopant redistribution due to the salicide process is proposed. The injection of vacancies and lattice strain during TiSi/sub 2/ formation causes defect-enhanced boron diffusion which results in a nonuniform lateral channel dopant redistribution and hence a threshold increase in short-channel devices. In addition to the small gate edge birds beak and the nonuniform oxidation-enhanced diffusion (OED) redistribution of channel dopant due to the polysilicon gate reoxidation, the self-aligned Ti silicide process can be major cause of the observed reverse short-channel effect in submicrometer MOSFET devices. >

Trench gate metal oxide semiconductor field effect transistor

Abstract: A trench gate MOS FET having one of the following features: a drain diffusion layer and/or a source diffusion layer having a two-layer structure consisting of a high concentration layer and a low concentration layer; at least a drain diffusion layer having a low concentration layer adjacent to the semiconductor surface of a trench gate and a high concentration layer adjacent to the low concentration layer; a gate oxide film formed to have a greater thickness at the overlapping portion of the diffusion layer and the gate electrode than at the other portions thereof; two trench gates provided on the semiconductor surface so as to control the conductivity of a channel region between the trench gates; or a trench isolation region provided on the semiconductor substrate in contact with the trench gate.

AlInAs-GaInAs HEMTs utilizing low-temperature AlInAs buffers grown by MBE

Abstract: Low-temperature AlInAs buffer layers incorporated in AlInAs-GaInAs HEMT epitaxial layers grown by MBE are discussed. A growth temperature of 150 degrees C followed by a short anneal is shown to eliminate kinks in the device I-V characteristic and sidegating and to reduce the output conductance dramatically. >

Field-effect transistor self-electrooptic effect device: integrated photodiode, quantum well modulator and transistor

Abstract: The authors propose and demonstrate the integration of a photodiode, a quantum-confined Stark-effect quantum-well optical modulator, and a metal-semiconductor field-effect transistor (MESFET) to make a field-effect transistor self-electrooptic effect device. This integration allows optical inputs and outputs on the surface of a GaAs-integrated circuit chip, compatible with standard MESFET processing. To provide an illustration of feasibility, the authors demonstrate signal amplification with a single MESFET. >

Merged bipolar and insulated gate transistors

Abstract: A vertical bipolar transistor is formed along with an IGFET transistor in a process in which the bipolar transistor collector, base and emitter structure is formed in the body of a semiconductor mesa-like structure while the IGFET transistor is formed in and along one of the sidewalls of the structure. Source and drain regions are formed in the structure by ion-implantation using a polysilicon gate electrode formed over a gate insulator on the sidewall as a self-aligning mask.

Method of making ultra dense dram cells

Abstract: This invention relates generally to dynamic random access, semiconductor memory arrays and more specifically relates to an ultra dense dynamic random access memory array. It also relates to a method of fabricating such arrays using a plurality of etch and refill steps which includes a differential etching step which is a key step in forming insulating conduits which themselves are adapted to hold a pair of field effect transistor gates of the adjacent transfer devices of one device memory cells. The differential etch step provides spaced apart device regions and an insulation region of reduced height between the trenches which space apart the memory cells. The resulting structure includes a plurality of rows of vertically arranged field effect transistors wherein the substrate effectively acts as a counterelectrode surrounding the insulated drain regions of each of the one device memory cells. A pair of gates are disposed in insulating conduits which run perpendicular to the rows of memory cells. Each gate in a conduit is disposed in insulated spaced relationship with a memory cell channel region which, in response to signals on the gate turns on a column of channel regions so as to permit the entry of charge into a selected storage region when a bitline associated with a particular cell is energized. The resulting array shows rows of pairs of memory cells wherein each cell of a pair is spaced from the other by a portion of the substrate acting as a counterelectrode and each of the pairs of memory cells is similarly separated from an adjacent pair by regions of conductive material acting as a counterelectrode.

Process for forming high and low voltage CMOS transistors on a single integrated circuit chip

Abstract: A process for forming both low voltage CMOS transistors and high voltage CMOS transistors on a common integrated circuit chip uses a common implantation and drive-in step to form both the n-type well of each PMOS transistor and the n-type drain extension well of each lightly doped drain (LDD) NMOS transistor and a separate implant and drive-in to form the p-type drain extension well of each LDD PMOS transistor.

Modeling of gate oxide shorts in MOS transistors

Abstract: A unified approach is proposed for modeling gate oxide shorts in MOS transistors using lumped-element models. These models take into account the possible structure of gate oxide short and the resulting changes that affect the I-V characteristics of MOS transistors. They can be used with the circuit simulator to predict the performance degradation of the VLSI circuit with gate oxide shorts. Demonstrated examples of models show close agreement with the experimental data. >

Vertical power mosfet having high withstand voltage and high switching speed

Abstract: In a vertical field effect transistor including a source electrode and a gate on the front surface of a semiconductor substrate having one conductivity type and a drain electrode on the back surface of the substrate, the semiconductor device of the present invention has the structure wherein a connection region of one conductivity type positioned between two channel forming base regions of the opposite conductivity type is formed by a semi­conductor layer having a higher impurity concentration than the drain region of the one conductivity type, and the surface portion of the connection region which is connected to the channel has a lower impurity concentration than the connection region.

Integrated bipolar-CMOS circuit isolation for providing different backgate and substrate bias

Abstract: Disclosed is a bipolar-CMOS circuit which includes a NMOS transistor site (18) electrically isolated from a bipolar transistor site (16). The NMOS transistor site (18) includes a semiconductor region (24) isolated from a bipolar transistor well (26) by deep diffusion ring (32). A buried layer (13) forms a bottom of the deep diffusion isolation ring (32). A backgate voltage can be applied to the isolated semiconductor region (24) of the NMOS device, which bias may be different than that applied to the substrate (10). Optimum performance of the NMOS transistor is thus assured irrespective of the magnitude of operating voltage of the bipolar transistor.