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Journal ArticleDOI

Analysis of the charge pumping technique and its application for the evaluation of MOSFET degradation

TLDR
In this article, a charge pumping technique is used to determine the degradation mechanisms in MOS transistors under all kinds of aging conditions (e.g., irradiation, hot-carrier, Fowler-Nordheim stress) and to quantify the degradation.
Abstract
It is shown that the charge pumping technique is able not only to determine the degradation mechanisms in MOS transistors under all kinds of aging conditions (eg, irradiation, hot-carrier, Fowler-Nordheim stress), but also in several cases to evaluate and to quantify the degradation It is further shown that the technique can be applied to separate the presence of fixed oxide changes due to charge trapping and the generation of interface traps It can be used to analyze degradations that occur uniformly over the transistor channel, as well as strongly localized transistor degradations (eg, for the case of hot-carrier degradations) All possible cases of uniform and nonuniform degradations, for p-channel as well as for n-channel transistors, are described, and for most of them experimental examples are given >

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Citations
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Journal ArticleDOI

Ultrathin (<4 nm) SiO2 and Si-O-N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

TL;DR: In this paper, the authors summarized recent progress and current scientific understanding of ultrathin (<4 nm) SiO2 and Si-O-N (silicon oxynitride) gate dielectrics on Si-based devices.
Journal ArticleDOI

Consistent model for the hot-carrier degradation in n-channel and p-channel MOSFETs

TL;DR: In this article, the degradation behavior of n-channel transistors under alternating injection conditions is discussed and fully explained based on the static stress degradation model for both channel types using the charge-pumping technique.
Journal ArticleDOI

Comments on "The generation and characterization of electron and hole traps created by hole injection during low gate voltage hot-carrier stressing of n-MOS transistors" [with reply]

TL;DR: Doyle et al. as discussed by the authors showed that neutral electron trap generation can occur in MOSFETs when large oxide fields occur during operation, and they concluded that electron traps are created during channel hot-hole injection and must be taken into consideration in hot carrier lifetime estimates under AC conditions.
Proceedings ArticleDOI

Hot-Carrier acceleration factors for low power management in DC-AC stressed 40nm NMOS node at high temperature

TL;DR: In this article, a three mode interface trap generation is proposed based on the energy acquisition involved in distinct interactions in all the V GS, V DS (V BS ) conditions as a single I DS lifetime dependence is observed with V GD > 0.
Journal ArticleDOI

Stress-induced oxide leakage

TL;DR: In this paper, a correlation between the leakage current and the charge-pumping current was evident in a series of voltage stress, annealing, and restress tests, suggesting that the leakage may be a result of the oxide-trap assisted tunneling.
References
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Journal ArticleDOI

A reliable approach to charge-pumping measurements in MOS transistors

TL;DR: In this article, a new and accurate approach to charge-pumping measurements for the determination of the Si-SiO 2 interface state density directly on MOS transistors is presented.
Journal ArticleDOI

Charge pumping in MOS devices

TL;DR: In this paper, gate pulses applied to MOS transistors were found to stimulate a net flow of charge into the substrate, and a charge-pumping phenomeonon was found in MOS gate-controlled-diode structures.
Journal ArticleDOI

Consistent model for the hot-carrier degradation in n-channel and p-channel MOSFETs

TL;DR: In this article, the degradation behavior of n-channel transistors under alternating injection conditions is discussed and fully explained based on the static stress degradation model for both channel types using the charge-pumping technique.
Journal ArticleDOI

MINIMOS&#8212;A two-dimensional MOS transistor analyzer

TL;DR: MINIMOS as discussed by the authors is a software tool for numerical simulation of planar MOS transistors, which is able to calculate doping profiles from the technological parameters specified by the user, and a new mobility model has been implemented which takes into account the dependence on the impurity concentration, electric field, temperature and especially the distance to the Si-SiO 2 interface.
Journal ArticleDOI

Analysis and modeling of floating-gate EEPROM cells

TL;DR: In this paper, a simplified device model is given based on the concept of coupling ratios, and experimental analysis of Write/ERASE characteristics for this type of memory cell are presented. But the authors do not consider the effect of positive charge trapping in the tunnel oxide and threshold window opening.
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