Showing papers on "Flip-flop published in 2013"

Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring Efficient Embedded Logic

Abstract: In this paper, we introduce a new dual dynamic node hybrid flip-flop (DDFF) and a novel embedded logic module (DDFF-ELM) based on DDFF. The proposed designs eliminate the large capacitance present in the precharge node of several state-of-the-art designs by following a split dynamic node structure to separately drive the output pull-up and pull-down transistors. The DDFF offers a power reduction of up to 37% and 30% compared to the conventional flip-flops at 25% and 50% data activities, respectively. The aim of the DDFF-ELM is to reduce pipeline overhead. It presents an area, power, and speed efficient method to incorporate complex logic functions into the flip-flop. The performance comparisons made in a 90 nm UMC process show a power reduction of 27% compared to the Semidynamic flip-flop, with no degradation in speed performance. The leakage power and process-voltage-temperature variations of various designs are studied in detail and are compared with the proposed designs. Also, DDFF and DDFF-ELM are compared with other state-of-the-art designs by implementing a 4-b synchronous counter and a 4-b Johnson up-down counter. The performance improvements indicate that the proposed designs are well suited for modern high-performance designs where power dissipation and latching overhead are of major concern.

Quantum Cost Optimization for Reversible Sequential Circuit

Abstract: Reversible sequential circuits are going to be the significant memory blocks for the forthcoming computing devices for their ultra low power consumption. Therefore design of various types of latches has been considered a major objective for the researchers quite a long time. In this paper we proposed efficient design of reversible sequential circuits that are optimized in terms of quantum cost, delay and garbage outputs. For this we proposed a new 3*3 reversible gate called SAM gate and we then design efficient sequential circuits using SAM gate along with some of the basic reversible logic gates.

Low-power 6-GHz wave-pipelined 8b x 8b multiplier

Abstract: In this study, a low-power, high-speed, layout-efficient 8 b × 8 b unsigned parallel multiplier based on pair-wise algorithm with wave-pipelining is introduced. Simplified interconnection and data propagation in forward direction with no feedback in pair-wise multiplication technique is the key to achieve high-performance wave-pipelined multiplier. In the proposed work, normal process complementary pass-transistor logic is used to build all the leaf cells of combinational block. The input/output registers are designed with high-performance pulse-triggered true single-phase clocking flip flop. Post-layout simulation with Taiwan Semiconductor Manufacturing Company Limited 0.18 μm single-poly double-metal complimentary metal oxide semiconductor technology using Tanner EDA V.13 shows that the proposed multiplier works at 6.25 GHz clock frequency and achieves the throughput of 6.25 billion multiplications per second with average power dissipation of 18.54 mW and overall latency of 3.24 ns at 25°C temperature and at 2 V supply rail.

A Beginning In The Reversible Logic Synthesis of Sequential Circuits

Abstract: A present reversible logic is one of the most crucial issues in modern technology. It has different areas for its application those are low power CMOS, nanotechnology, quantum computing, cryptology optical computing DNA computing digital signal processing (DSP), Quantum dot cellular automatic communication, computer graphics. The main purposes of designing reversible logic are to decrease quantum cost. This paper proposed a design of reversible sequential circuits (RS Flip Flop, JK Flip Flop, D Flip Flop, T Flip Flop). The novelty of the paper is proposed design are better than the existing proposed one in terms of reversible gates.

SEU Hardened Flip-Flop Based on Dynamic Logic

Abstract: A conventional master-slave flip-flop is very sensitive to particle strike that causes an SEU. When the clock is high, an SEU may upset the logic state of the master latch resulting in a faulty output of this flip-flop, and the erroneous value will also be locked in the slave latch when clock is low. When the clock is low, an SEU may also upset the logic state of the slave latch, resulting in a faulty output of this flip-flop. This paper presents an SEU hardened flip-flop that can mitigate SEU using an error detection circuit and a multiplexer. When the clock is high or low, an SEU in the master or slave latch of a flip-flop can be detected by the error detection circuit using dynamic logic. The multiplexer selects a correct output according to the error indication signal. The proposed flip-flop has small area, power and delay overheads and good radiation hardening capabilities.

Organic Complementary Logic Circuits and Volatile Memories Integrated on Plastic Foils

Abstract: This paper presents organic based logic and memory circuits. All those circuits are made with organic N- and P-type transistors. Organic complementary NAND and NOR gates were characterized and show performance equivalent to or better than the literature-reported ones. The presented memory circuits include an SRAM memory point and an edge-triggered flip-flop. The flip-flop is made of six organic two-input and three-input NAND gates, representing a total of 26 organic transistors for a surface of 170 mm2. The maximum operating frequency of this flip-flop is 220 Hz under a supply of ±20 V. All the circuits were manufactured using a standard organic sheet-to-sheet process in ambient air. Electrical characteristics remain identical after repeated measurements. Finally, a model matching the presented circuits' behavior was carried out, permitting the design of more complex circuits.

New D-Flip-Flop Design in 65 nm CMOS for Improved SEU and Low Power Overhead at System Level

Abstract: A new latch architecture based on a switchable hysteresis mechanism to improve the SEU hardness in hold mode and limit the delay penalty during write operation is proposed. This latch relies on the Schmitt trigger inverter schematic and has been named the Robust Schmitt Trigger (RST) latch. RST latch has been implemented in a 65 nm radiation test vehicle and upset rates have been measured during proton irradiations. Our design solution enhanced the SEU cross-section and divides by 2 the system level power consumption penalty compared to a DICE based design. The RST latch is an alternative between the DICE latch and the reference latch for soft radiative environments.

Low Power CMOS Counter Using Clock Gated Flip-Flop

Abstract: gated flip-flop is presented in this paper. The circuit is based on a new clock gating flip flop approach to reduce the signal's switching power consumption. It has reduced the number of transistors. The proposed flip-flop is used to design 10 bits binary counter. This counter has been designed up to the layout level with 1V power supply in 90nm CMOS technology and have been simulated using Microwind simulations. Simulations have shown the effectiveness of the new approach on power consumption and transistor count

PCRAM Flip-Flop Circuits with Sequential Sleep-in Control Scheme and Selective Write Latch

Abstract: In this paper, two new flip-flop circuits with PCRAM latches that are FF-1 and FF-2, respectively, are proposed not to waste leakage during sleep time. Unlike the FF-1 circuit that has a normal PCRAM latch, the FF-2 circuit has a selective write latch that can reduce the switching activity in writing operation to save switching power at sleep-in moment. Moreover, a sequential sleep-in control is proposed to reduce the rush current peak that is observed at the sleep-in moment. From the simulation of storing ‘000000’ to the PCRAM latch, we could verify that the proposed FF-1 and FF-2 consume smaller power than the conventional 45-nm FF if the sleep time is longer than 465 μs and 95 μs, respectively, at 125°C. For the rush current peak, the sequential sleep-in control could reduce the current peak as much as 77%.

In-placement clock-tree aware multi-bit flip-flop generation for power optimization

Abstract: Utilizing multi-bit flip-flops (MBFFs) is one of the most effective power optimization techniques in modern nanometer integrated circuit (IC) design. Most of the previous work apply MBFFs without doing placement refinement of combinational logic cells. Such problem formulation may result in less power reduction due to tight timing constraints with fixed combinational logic cells. This paper introduces a novel placement flow with clock-tree aware flip-flop merging and MBFF generation, and proposes the corresponding algorithms to simultaneously minimize flip-flop power and clock latency when applying MBFFs during placement. Experimental results based on the IWLS-2005 benchmark show that our approach is very effective in not only flip-flop power but also clock latency minimization without degrading circuit performance. To our best knowledge, this is also the first work in the literature which considers clock trees during flip-flop merging and MBFF generation.

Flip-flop for reducing dynamic power

Abstract: A flip-flop circuit may include a first latchand a second latch. The first latch, which may operate as a "master" latch, includes a first input terminal to receive a data signal, a second input terminal to receive a clock signal, and an output terminal. The second latch, which may operate as a "slave" latch, includes a first input terminal connected directly to the output terminal of the first latch, a second input terminal to receive the clock signal, and an output terminal to provide an output signal. The first latch and the second latch are to be clocked on the same phase of the clock signal, thereby eliminating the need to include clock inversion circuits that generate complementary clock signals.

Positive edge preset reset flip-flop with dual-port slave latch

Abstract: In an embodiment, a flip-flop circuit contains a 2-input multiplexer (102), a master latch 9104), a transfer gate (106) and a slave latch (108). The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SSN and PREN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Rigorous simulation study of a novel non-volatile magnetic flip-flop

Abstract: The ever increasing demand in fast and cheap bulk memory as well as electronics in general has driven the scaling efforts in CMOS since its very beginnings. Today, pushing the limits of integration density is still a major concern, but gradually power efficient computing gains more and more interest. A possible way to reduce power consumption is to introduce non-volatility into the devices. Thus power is consumed only, when information is written or read out, while the rest of the time the devices preserve the information with out any power demand. In this work we propose a novel non-volatile magnetic flip-flop which shifts the actual logic operation from the electric signal domain to the magnetic domain, operating via constructive and destructive superposition of spin waves generated by the spin transfer torque effect. Furthermore we carried out a rigorous simulation study for three different device sizes and found them operational between ≈4×1010A/m2 and ≈1012A/m2 at switching times from tens of nanoseconds to picoseconds.

High-performance low leakage power consumption master-slave type D flip-flop

Abstract: The invention discloses a high-performance low leakage power consumption master-slave type D flip-flop. The high-performance low leakage power consumption master-slave type D flip-flop is characterized by comprising a clock signal inverter circuit, a master latch circuit, a slave latch circuit, an N-channel metal oxide semiconductor (NMOS) pipe power control switch, a P-channel Metal Oxide Semiconductor (PMOS) pipe power control switch and a maintaining inverter. The clock signal inverter circuit is connected with the master latch circuit, the clock signal inverter circuit is connected with the slave latch circuit, the master latch circuit is connected with the slave latch circuit, the slave latch circuit is connected with the maintaining inverter, the maintaining inverter is connected with the PMOS pipe power control switch, the clock signal inverter circuit, the master latch circuit and the slave latch circuit are all connected with the NMOS pipe power control switch, and the maintaining inverter is connected with the PMOS pipe power control switch. The high-performance low leakage power consumption master-slave type D flip-flop has the advantages of being simple in circuit structure, small in the number of transistors, simple in timing sequence switching of a normal working state and a sleep mode, good in working performance, low in dynamic power consumption and leakage power consumption, and suitable for being used as a standard cell of a digital circuit to be applicable to the design of a low power consumption integrated circuit in deep submicron complementary metal-oxide-semiconductor transistor (CMOS) process.

Note: A very simple circuit for piezo actuator pseudo-tracking for continuous-wave cavity ring-down spectroscopy.

Abstract: A very simple circuit for pseudo-tracking of the piezo actuator for continuous-wave cavity ring-down spectroscopy (cw-CRDS) is presented. The circuit is based on an ordinary positive-edge trigger D-type flip flop integrated circuit, has a low parts count, and can be easily assembled using only off the shelf components. The circuit can be straightforwardly incorporated into most cw-CRDS setups and, thanks to the increased ring-down event rate, higher sensitivity or lower data acquisition time can be achieved.

A high performance D-flip flop design with low power clocking system using MTCMOS technique

Abstract: Power consumption plays an important role in any integrated circuit and is listed as one of the top three challenges in International technology roadmap for semiconductors. In any integrated circuit, clock distribution network and flip -flop consumes large amount of power as they make maximum number of internal transitions. In this paper, various techniques for implementing flip-flops with low power clocking system are analyzed. Among those techniques clocked pair shared flip-flop (CPSFF) consume least power than conditional data mapping flip flop (CDMFF), conditional discharge flip flop (CDFF) and conventional double edge triggered flip-flop (DEFF). We propose a novel CPSFF using Multi-Threshold voltage CMOS (MTCMOS) technique which reduces the power consumption by approximately 20% to 70% than the original CPSFF. In addition, to build a clocking system, double edge triggering and low swing clocking can be easily incorporated into the new flip-flop.

Achieveing reduced area by Multi-bit Flip flop design

Abstract: Timing Optimization is one of the most important objectives of the designer in the Modern VLSI world. Memory elements play a vital role on Digital World. The basic memory elements of designer considerations are Latch and flip flop. In this paper, we analyze the design of Single-bit Flipflop (SBFF) and made performance comparison over the Multi-bit Flip-flop (MBFF). For improving Flip flop performance one of the promising way is to merge the clock pulse. The Multi-bit Flip-flop is designed by single clock pulse and achieves same functionality like two single-bit Flip-flop. A shift register is designed using both Single-Bit Flip-Flop (SBFF) and Multi-Bit Flip-Flop (MBFF). This paper analyzes the timing performance of both SBFF and MBFF in Xilinx Virtex-5 family (XC5VLX50). These results in favor of Multi-Bit Flip-Flop as reduction of Clock network such as clock buffer and gate delay.

High density low power scan flip-flop

Abstract: A scan flip flop includes a partial multiplexer coupled to a master latch. The partial multiplexer is configured to receive a scan enable (SCAN) where the partial multiplexer includes an OR gate coupled to a tri-stated AND gate. A tri-state inverter is coupled to an output of the master latch and a slave latch is configured to receive an output of the tri-state inverter. A delay element is coupled to the slave latch, where the delay element is configured to delay a first output of the slave latch in response to the scan enable to generate a dedicated scan output.

Design and analysis of high speed shift register using Single clock pulse method

Abstract: Today's electronic devices move drastically towards high speed design feature. The traditional D-flip flop is no longer suitable for designing shift registers because of its low-speed performance. Many different types of shift registers, such as Universal Shift registers, Serial In Serial Out, Serial In Parallel Out, Parallel In Parallel Out and Parallel In Serial Out have been developed. Also, there are many low-power shift register design techniques that have been proposed. However, they are all lagging behind in high speed performances. The shift register design using Single clock pulse with Hold Mode (HM-FF) & without Hold Mode (WHM-FF) Flip Flop can be a potential solution to this problem. The shift register design using this proposed method promises to achieve tremendous improvements in performance of speed. When compared to its conventional counterparts, the proposed design is able to attain more than 41.9% reduction in over all time delay, which is targeted to Xilinx Virtex 6 devices.

Master slave flip-flop with low power consumption

Abstract: In a master-slave flip-flop, the master latch has first and second three-state stages, and a first feedback stage. The slave latch has third and fourth three-state stages, and a second feedback stage. First and second clock switches having opposite phases are provided. The first clock switch is configured in one of the first and fourth three-state stages, and the other stage shares the first clock switch. The second clock switch is configured in one of the second and third three-state stages, and the other stage shares the second clock switch. The second three-state stage has an additional pair of complementary devices having signal paths connected in series with each other with both being gated by a data output of the slave latch. The flip-flop reduces the number of clock switches and clock switch power consumption.

Novel MTJ-based shift register for non-volatile logic applications

Abstract: The increasing costs and leakage losses have become the major concerns for CMOS technology scaling. A possible way to address in particular the standby power problem is to introduce non-volatility into the devices and circuit blocks so that unused devices or even entire circuit blocks do not waste energy, and power is only spent, when information is read or written. Recently, we proposed a non-volatile magnetic flip flop which moves the information storage and processing from the CMOS domain to the magnetic domain. Here, we propose a way to extend the functionality of the device to a shift register; computing via spin wave superposition and passing information by spin torque transfer (STT). The presented shift register and its operation allows an extremely dense layout, is CMOS compatible, and non-volatile.

Dual-Edge Triggered T Flip-Flop Structure Using Quantum-Dot Cellular Automata

Abstract: As an emerging nanotechnology, quantum-dot cellular automata (QCA) has the potential to be used for next generation VLSI. Various designs of combinational logic circuits have been proposed for QCA implementation, but sequential circuit design is limited due to the lack of high-performance QCA flip-flops. After an introduction on QCA and dual-edge triggered (DET) flip-flops, a new QCA DET T flip-flop following a pulsed latch scheme is presented. The proposed T flip-flop is simulated using QCADesigner simulator and its logic functionality is verified. The same data throughput of the DET flip-flop can be achieved while operating at half the clock frequency of a single-edge triggered (SET) counterpart. The proposed flip-flop is promising in building QCA sequential circuits with low power and high performance.

Negative edge flip-flop with dual-port slave latch

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch Control signals RET and RETN determine when data is stored in the slave latch during retention mode

On-chip probe circuit for detecting faults in an FPGA

Abstract: An integrated programmable logic circuit having a read/write probe includes a plurality of programmable logic circuits having internal circuit nodes and a plurality of flip flops, each having an asynchronous data input line, an asynchronous load line, and a data output connected to an internal circuit node, a probe-data line, an address circuit for selecting one of the internal circuit nodes, a read-probe enable line for selectively coupling the selected one of the internal circuit nodes to the probe-data line, a data input path to the asynchronous data input line of each flip flop, a write-probe data input path to the asynchronous data input line of each flip flop, a write-probe enable line, and selection circuitry, responsive to the address circuit and the write-probe enable line, to couple one of the data input path and the write-probe data input path to the asynchronous data input of a selected flip flop.

Quaternary edge-triggered flip-flop with neuron-MOS literal circuit

Abstract: A novel CMOS quaternary D-type edge-triggered flip-flop using a single latch with neuron-MOS literal circuits is presented. In the proposed circuit, data are sampled into the latch during a short transparency period for rising edge of the clock signal by using the arrow pulse produced by the race-hazard of the clock signal. The quaternary literal functions are realized by using neuron-MOS transistors without any modification of the thresholds. The benefit of the proposed voltage-mode quaternary flip-flop is that the circuit can be fabricated by standard CMOS process with a 2-ploy layer. Besides, it has a simpler construction with respect to previously reported quaternary flip-flop. The effectiveness of the proposed circuit has been validated by HSPICE simulation results with TSMC 0.35μm 2-ploy 4-metal CMOS technology.

Design of a low-power pulse-triggered flip-flop with conditional clock technique

Abstract: Flip-flops are basic sequential elements in digital circuits and they have a deep impact on the performance of the circuits. In order to reduce the redundant transitions at internal nodes of the flip-flop, a conditional clock technique is proposed, and then a conditional clock pulse-triggered flip-flop (CCFF) based on this technique is designed. In CCFF, the clock is blocked when the input remains unchanged so that the internal nodes will not switch with the clock, which reduces the power consumption effectively. Based on the TSMC 0.18μm technology, the post-layout simulation results show that the proposed CCFF has an obvious advantage in power consumption when the data switching activity factor is below 50% as compared with other state-of-the-art pulse-triggered flip-flops, and the power saving is more than 50% when the activity factor is 10%.

Flip-flop circuit

Abstract: A flip-flop circuit has a master latch circuit and a slave latch circuit. In the flip-flop circuit, the master latch circuit and the slave latch circuit share at least a pair of transistors. In response to the clock signal, the signal held in the master latch circuit can be output at higher speed as the output signal via the intermediate node, the slave latch circuit and the output circuit. The flip-flop circuit can be reduced in cell size and improved in processing speed.

Positive Feed Back Adiabatic Logic: PFAL Single Edge Triggered Semi-Adiabatic D Flip Flop

Abstract: 2 Abstract: The technical constraints and market demands necessitated the urgency of efforts in development of low power circuits. Researchers are exploring all the different factors which affect the low power equations for the circuit. All these being realistic parameters have limits of their optimization. The device scaling, capacitance reduction, voltage scaling, activity factor improving using different set of encoding, speed performance constraints etc. have their physical limitations. Yet, their limiting values are near, but still debatable, with the progress of technology and tremendous amount of efforts all over the world by the researchers. In the scenario many researchers are trying to adopt different optimization and energy conservation principles for VLSI circuit design. The problem formulation is made in accordance, matching with the platform of other engineering fields and transforming, resolving and optimizing them to extract the desired power aware design with benefits attaining from the classical approach. Utilizing the concepts and fundamentals of adiabatic theory in mechanics for formulating the VLSI circuit design problems comes into such an efforts proposed and backed by several researchers. The basic principle in adiabatic logic circuits is to slow down the logic transition varying from logic 1 to logic 0 and vice versa, aiming in reducing the power dissipation. Many different approaches/ techniques are proposed for implementing adiabatic logic circuits. PFAL is one of these techniques which positively promise assisting in the power issues. This paper presents a dual rail, semi adiabatic PFAL D flip flop. Master slave configuration is used for implementing the positive edge flip flop. The basic buffer/inverter configuration is used for driving the functionality of the D flip flop after integrating extra transistors. Tanner ECAD tool is used for simulation and verification the circuit with 1.25 micron technology. The power dissipation for the circuit is 3.50E-02.

Nonvolatile flip-flop based on pseudo-spin-transistor architecture and its nonvolatile power-gating applications for low-power CMOS logic

Abstract: We computationally analyzed performance and power-gating (PG) ability of a new nonvolatile delay flip-flop (NV-DFF) based on pseudo-spin-MOSFET (PS-MOSFET) architecture using spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The high-performance energy-efficient PG operations of the NV-DFF can be achieved owing to its cell structure employing PS-MOSFETs that can electrically separate the STT-MTJs from the ordinary DFF part of the NV-DFF. This separation also makes it possible that the break-even time (BET) of the NV-DFF is designed by the size of the PS-MOSFETs without performance degradation of the normal DFF operations. The effect of the area occupation ratio of the NV-DFFs to a CMOS logic system on the BET was also analyzed. Although the optimized BET was varied depending on the area occupation ratio, energy-efficient fine-grained PG with a BET of several sub-microseconds was revealed to be achieved. We also proposed microprocessors and system-on-chip (SoC) devices using nonvolatile hierarchical-memory systems wherein NV-DFF and nonvolatile static random access memory (NV-SRAM) circuits are used as fundamental building blocks.

Triangular Power Supply Based Adiabatic Logic Family

Abstract: This paper presents the design and performance evaluation of a modified complementary energy path adiabatic logic (MCEPAL) circuit. A simulative investigation on the proposed MCEPAL based, multiplexer, JK flip flop and 3 bit counter has been done using VIRTUOSO SPECTRE simulator of cadence in 0.18µm UMC technology and its performance has been compared with the previous adiabatic (i.e. CEPAL) multiplexer, JK flip flop and 3 bit counter circuits. The MCEPAL based, multiplexer, JK flip flop and 3 bit counter circuit exhibits the power saving of 77%, 25% and 48% respectively to its corresponding CEPAL circuits at 100 MHz frequency and 1.8V operating voltage.