Showing papers on "Gate driver published in 2012"

A New Multilevel Converter Topology With Reduced Number of Power Electronic Components

Abstract: In this paper, a new topology for cascaded multilevel converter based on submultilevel converter units and full-bridge converters is proposed. The proposed topology significantly reduces the number of dc voltage sources, switches, IGBTs, and power diodes as the number of output voltage levels increases. Also, an algorithm to determine dc voltage sources magnitudes is proposed. To synthesize maximum levels at the output voltage, the proposed topology is optimized for various objectives, such as the minimization of the number of switches, gate driver circuits and capacitors, and blocking voltage on switches. The analytical analyses of the power losses of the proposed converter are also presented. The operation and performance of the proposed multilevel converter have been evaluated with the experimental results of a single-phase 125-level prototype converter.

Analysis and Design of a Bidirectional Isolated DC–DC Converter for Fuel Cells and Supercapacitors Hybrid System

Abstract: Electrical power systems in future uninterruptible power supplies or electrical vehicles may employ hybrid energy sources, such as fuel cells and supercapacitors. It will be necessary to efficiently draw the energy from these two sources as well as recharge the energy storage elements by the dc bus. In this paper, a bidirectional isolated dc-dc converter controlled by phase-shift angle and duty cycle for the fuel-cell hybrid energy system is analyzed and designed. The proposed topology minimizes the number of switches and their associated gate driver components by using two high-frequency transformers that combine a half-bridge circuit and a full-bridge circuit together on the primary side. The voltage doubler circuit is employed on the secondary side. The current-fed input can limit the input current ripple that is favorable for fuel cells. The parasitic capacitance of the switches is used for zero voltage switching (ZVS). Moreover, a phase-shift and duty-cycle modulation method is utilized to control the bidirectional power flow flexibly and it also makes the converter operate under a quasi-optimal condition over a wide input voltage range. This paper describes the operation principle of the proposed converter, the ZVS conditions, and the quasi-optimal design in depth. The design guidelines and considerations regarding the transformers and other key components are given. Finally, a 1-kW 30~50-V-input 400-V-output laboratory prototype operating at 100-kHz switching frequency is built and tested to verify the effectiveness of the presented converter.

An Experimentally Verified Active Gate Control Method for the Series Connection of IGBT/Diodes

Abstract: The series connection of insulated gate bipolar transistor (IGBT)/diode devices allows the operation at voltage levels higher than the rated voltage of one IGBT/diode. However, due to individual parameter differences of the series-connected IGBT/diodes, it is difficult to ensure a proper voltage balance between them, and transient or steady-state voltage unbalances could cause the failure of these devices. This paper presents an active gate driver developed by the authors that is suitable for the series connection of IGBTs. The proposed active gate driver achieves the transient and steady-state voltage balance between the series-connected IGBT/diode devices. The effectiveness of the gate driver and the active gate control method has been experimentally validated, and promising results have been obtained.

Analysis of the switching speed limitation of wide band-gap devices in a phase-leg configuration

Abstract: Advanced power semiconductor devices, especially wide band-gap devices, have inherent capability for fast switching. However, due to the limitation of gate driver capability and the interaction between two devices in a phase-leg during switching transient (cross talk), the switching speed is slower than expected in practical use. This paper focuses on identifying the key limiting factors for switching speed. The results provide the basis for improving gate drivers, eliminating interference, and boosting switching speed. Based on the EPC2001 Gallium Nitride transistor, both simulation and experimental results verify that the limiting factors in the gate loop include the pull-up (-down) resistance of gate driver, rise (fall) time and amplitude of gate driver output voltage; among these the rise (fall) time plays the primary role. Another important limiting factor of device switching speed is the spurious gate voltage induced by cross talk between two switches in a phase-leg. This induced gate voltage is not only determined by the switch speed, but also depends on the gate loop impedance, junction capacitance, and operating conditions of the complementary device.

Optimal Design of a Push-Pull-Forward Half-Bridge (PPFHB) Bidirectional DC–DC Converter With Variable Input Voltage

Abstract: This paper presents a low-cost bidirectional isolated dc-dc converter, derived from dual-active-bridge converter for the power sources with variable output voltage like super capacitors. The proposed converter consists of push-pull-forward circuit half-bridge circuit (PPFHB) and a high-frequency transformer; this structure minimizes the number of the switching transistors and their associate gate driver components. With phase-shift control strategy, all the switches are operated under zero-voltage switching (ZVS) condition. Furthermore, in order to optimize the converter performance and increase efficiency, optimal design methods and criteria are investigated, including coupled inductors design, bidirectional power flow analysis, harmonics analysis, and ZVS range extension. Based on all the optimal parameters, higher efficiency can be achieved. Finally, prototypes are built in laboratory controlled by digital signal processor for comparison purpose. Detailed test results verify the theoretical analysis and demonstrate the validity of optimization design method.

A multilevel inverter with reduced number of switches

Abstract: A multilevel inverter is a power electronic device that is used for high voltage and high power applications, with the added advantages of low switching stress and lower total harmonic distortion (THD), hence reducing the size and bulk of the passive filters. This paper proposes a new topology of a cascaded multilevel inverter that utilizes less number of switches than the conventional topology. Therefore with less number of switches in the circuit, there will be a reduction in the gate driver circuits and also in effect fewer switches will be conducting for specific intervals of time. The circuitry consists of smaller multilevel inverter blocks connected in series to achieve its characteristic output waveform. A seven level inverter will be simulated with the implementation of PWM techniques and its effect on the harmonic spectrum will be analyzed. The system will be modelled with the help of MATLAB/SEVIULINK.

Novel AC-Coupled Gate Driver for Ultrafast Switching of Normally Off SiC JFETs

Abstract: Over the last years, more and more SiC power semiconductor switches have become available in order to prove their superior behavior. A very promising device is the 1200 V 30 A JFET manufactured by SemiSouth. It features a very low on-resistance per die area (2.8 mΩ-cm2), switching within 20 ns, normally off characteristic, high-temperature operation and has already been commercialized in contrast to many other SiC switches. To fully exploit the potential of the SiC normally off JFET, conventional gate drivers for unipolar devices must be adapted to this device due to its special requirements. During on-state, the gate voltage must not exceed 3 V, while a current of around 300 mA (depending on the desired on-resistance) must be fed into the gate; during switching operation, the transient gate-source voltage should be around ±15 V and the low threshold voltage of less than 0.7 V requires a high noise immunity which is a severe challenge as the device has a comparably low gate-source but high gate-drain capacitance. To meet these requirements, several concepts have been published recently. They deal with the challenges mentioned, but they still show certain limitations (e.g., frequency and duty cycle limitations or need for additional cooling due to high gate driver losses). In this paper, a novel gate driver consisting of only one standard gate driver IC, resistors, capacitors, and diodes is designed and experimentally validated. It supplies enough gate current for minimum on-resistance, allows fast switching operation, features a high noise immunity, and can be used for any duty cycle and typical switching frequencies without significant self-heating.

A 200-MHz Integrated Buck Converter With Resonant Gate Drivers for an RF Power Amplifier

Abstract: High switching frequency dc-dc converters are present in many applications where wide regulation bandwidth and high efficiency are needed A resonant gate driver is presented for improvement of efficiency at light-to-medium load conditions Gate power losses that are a main contributor to total losses are reduced thanks to energy recovery A testchip designed in 025- BiCMOS shows as much as a 30% decrease in power losses compared to a conventional driver at 200-MHz switching frequency The proposed resonant gate driver is fully integrated with its inductor unlike earlier works The limitation in the reduction of gate losses is detailed and confirmed experimentally

A 2.5 kV Isolation 35 kV/us CMR 250 Mbps Digital Isolator in Standard CMOS With a Small Transformer Driving Technique

Abstract: A small-size on-chip transformer-based digital isolator for power control systems is proposed. With a proposed pulse generation and detection scheme that enables a 5 V standard CMOS transistor to utilize GHz-band signals, transformer area is reduced to 1/4-1/8 that of conventional transformers. A test chip achieves a 2.5 kV isolation voltage, a 35 kV/us CMR, a 1.6 mA static current and a 250 Mbps data rate, all which are equal to or superior to those of optocouplers or conventional digital isolators. The developed technology greatly reduces the number of chips in power control systems by allowing integration of multiple isolators in a CMOS chip together with microcontrollers or gate drivers. Moreover, the high-speed low-power capability expands the application potential to include isolated serial links, controller area network (CAN), FlexRay, medical devices, displays, sensors, etc.

Performance evaluation of SiC power MOSFETs for high-temperature applications

Abstract: In this paper, the high-temperature performance of the commercial SiC power MOSFETs has been extensively evaluated beyond 125 °C - the maximum junction temperature according to the datasheet. Both the static and switching characteristics have been measured under various temperatures up to 200 °C. The results show the superior electrical performance of the SiC MOSFETs for high-temperature operation. Meanwhile, the gate biasing and gate switching tests have also been conducted to test the gate oxide reliability of these devices under elevated temperatures. The test results reveal the degradation in the device characteristics under high temperature and different gate voltage conditions, which exhibit the trade-off between the performance and the reliability of SiC MOSFETs for high-temperature applications.

A 200 °C Universal Gate Driver Integrated Circuit for Extreme Environment Applications

Abstract: High-temperature power converters (dc-dc, dc-ac, etc.) have enormous potential in extreme environment applications, including automotive, aerospace, geothermal, nuclear, and well logging. For successful realization of such high-temperature power conversion modules, the associated control electronics also need to perform at high temperature. This paper presents a silicon-on-insulator (SOI) based high-temperature gate driver integrated circuit (IC) incorporating an on-chip low-power temperature sensor and demonstrating an improved peak output current drive over our previously reported work. This driver IC has been primarily designed for automotive applications, where the underhood temperature can reach 200 °C. This new gate driver prototype has been designed and implemented in a 0.8 μm, 2-poly, and 3-metal bipolar CMOS-DMOS (Double-Diffused Metal-Oxide Semiconductor) on SOI process and has been successfully tested for up to 200 °C ambient temperature driving a SiC MOSFET and a SiC normally-ON JFET. The salient feature of the proposed universal gate driver is its ability to drive power switches over a wide range of gate turn-ON voltages such as MOSFET (0 to 20 V), normally-OFF JFET (-7 to 3 V), and normally-ON JFET (-20 to 0 V). The measured peak output current capability of the driver is around 5 A and is thus capable of driving several power switches connected in parallel. An ultralow-power on-chip temperature supervisory circuit has also been integrated into the die to safeguard the driver circuit against excessive die temperature (≥220 °C). This approach utilizes increased diode leakage current at higher temperature to monitor the die temperature. The power consumption of the proposed temperature sensor circuit is below 10 μW for operating temperature up to 200 °C.

Apparatus and method for driving liquid crystal display device

Abstract: An apparatus and method for driving an image display device are disclosed. The disclosed driving apparatus and method achieve synchronous driving of driving integrated circuits for driving an image display panel, through internal generation of drive control signals, thereby preventing a degradation in picture quality caused by erroneous driving timing while achieving an enhancement in product reliability. The driving apparatus includes a display panel, which includes a plurality of pixel regions, to display an image, a plurality of data integrated circuits, which share at least one of synchronizing signals internally generated therefrom, generate gate and data control signals in accordance with the shared synchronizing signal, and drive data lines of the display panel, using the internally-generated data control signals, and a gate driver for driving gate lines of the display panel in accordance with the gate control signal generated from one of the plural data integrated circuits.

High-Temperature Silicon-on-Insulator Gate Driver for SiC-FET Power Modules

Abstract: Silicon Carbide (SiC) power semiconductors have shown the capability of greatly outperforming Si-based power devices. Faster switching and smaller on-state losses coupled with higher voltage blocking and temperature capabilities make SiC an attractive semiconductor for high-performance, high-power-density power modules. However, the temperature capabilities and increased power density are fully realized only when the gate driver needed to control the SiC devices is placed next to them. This requires the gate driver to successfully operate under extreme conditions with reduced or no heat sinking requirements. In addition, since SiC devices are usually connected in a half- or full-bridge configuration, the gate driver should provide electrical isolation between the high- and low-voltage sections of the driver itself. This paper presents a 225°C operable, silicon-on-insulator (SOI) high-voltage isolated gate driver IC for SiC devices. The IC was designed and fabricated in a 1 μm, partially depleted, CMOS process. The presented gate driver consists of a primary and a secondary side which are electrically isolated by the use of a transformer. The gate driver IC has been tested at a switching frequency of 200 kHz at 225°C while exhibiting a dv/dt noise immunity of at least 45 kV/μs.

Design and Development of Very High Frequency Resonant DC–DC Boost Converters

Abstract: This paper presents a very high frequency dc-dc boost converter. This design features low voltage stress on the switch, high efficiency, and simple control. The low energy storage requirements provide a more effective integration. A proposed resonant gate driver provides variable duty cycle and possibility of the control of the converter at very high frequencies. A 60-MHz prototype of the proposed converter is designed and implemented. Experimental results demonstrate the effectiveness of the proposed control strategy.

A DC-isolated gate drive IC with drive-by-microwave technology for power switching devices

Abstract: Outstanding GaN-based HFETs (HFET: Heterojunction Field-Effect Transistors) [1] power devices are expected to replace all Si power devices in high power applications such as inverter systems due to their excellent performance In order to exploit the full potential of such emerging GaN power devices, the gate driver that controls the device by a pulse width modulation (PWM) signal is becoming more important The vital function of the gate driver is to provide an isolated gate signal against the reference source voltage that operates at high voltage In addition to this function, their integration with GaN power HFETs is also desirable to achieve smaller system size, lower cost and user-friendliness Although there are several signal isolation techniques for a gate driver such as to use a photo-coupler and wireless pulse transformer [2], these techniques have disadvantages such as large system size and difficulty in integration Other bootstrap or charge pump techniques [3] in high voltage gate drivers (HVIC) have been developed to generate a reference voltage, but the driver can only be used in particular applications such as inverters Meanwhile, we have focused our attention on the recent technology of wireless power transmission using an electromagnetic resonant coupler (EMRC) [4] with an open-ring resonator [5], which is very attractive due to its high efficiency in power transmission and its compactness at high frequency

A novel gate assist circuit for quick and stable driving of SiC-JFETs in a 3-phase inverter

Abstract: A novel gate drive circuit for an SiC-JFET in a bridge circuit that ensures a quick and stable switching has been proposed and demonstrated. The gate voltage of an off-state transistor tends to rise up due to a steep drain-source voltage change caused by turning-on of the transistor in the other side of the bridge circuit. Even though the gate terminal is kept in the off-state by a voltage source, the abovementioned steep voltage change induces a non-off-state voltage across the parasitic inductance in the gate wiring. As a result, the capability of an SiC transistor for high switching speed in a bridge circuit is limited. The novel gate assist circuit using a PNP transistor with additional capacitors can overcome this limit. It was verified experimentally that the new gate assist circuit improves the turn-on delay time by approximately six fold and the turn-off time by 72%.

Dynamic Mosfet Gate Drivers

Abstract: The embodiments herein describe a dynamic metal-oxide-semiconductor field-effect transistor (MOSFET) gate driver system architecture and control scheme. The MOSFET gate driver system dynamically adjusts both the gate driver turn-on-resistance and the gate driver turn-off resistance within a single (i.e., one) switching cycle to reduce electromagnetic interference (EMI) in the system and to minimize the conduction loss of a power MOSFET during operation.

Low-Power Gate Driver Circuit for TFT-LCD Application

Abstract: This paper presents a novel low-power gate driver circuit fabricated from glass by using hydrogenated amorphous silicon (a-Si:H) technology and a standard five-mask process. The tolerance of the threshold voltage shift of the proposed gate driver circuit can be estimated as 30 V by using an H-SPICE simulator. Measurement results indicate that the rising and falling times of the output waveform are equal to those in the initial state. Moreover, the proposed gate driver circuit can operate reliably at a high temperature (T = 120 °C) for over 360 h. Furthermore, the proposed gate driver circuit reduces power consumption by 77.3% over that of a conventional gate driver circuit.

A New High Efficiency Current Source Driver With Bipolar Gate Voltage

Abstract: A novel bipolar current source driver (CSD) for power MOSFETs is proposed in this paper. The proposed bipolar CSD alleviates the gate current diversion problem of the existing CSDs by clamping the gate voltage to a flexible negative value (such as -3.5 V) during turn-off transition. Therefore, the proposed driver is able to turn off the MOSFET much faster with a higher effective gate current. The idea presented in this paper can also be extended to other CSDs to further improve the efficiency with high output currents. The experimental results verify the benefits of the proposed CSD. For buck converters with 12 V input at 1 MHz switching frequency, the proposed driver improves the efficiency from 80.5% using the existing CSD to 82.5% (an improvement of 2%) at 1.2 V/30 A, and at 1.3 V/30 A output, from 82.5% using the existing CSD to 83.9% (an improvement of 1.4%).

Power transistor gate driver

Abstract: The present invention relates to a gate driver for a power transistor comprising a first charging path operatively connected between a first voltage supply and a gate terminal of the power transistor for charging the gate terminal to a first gate voltage. A second charging path is connectable between the gate terminal of the power transistor and a second supply voltage to charge the gate terminal from the first gate voltage to a second gate voltage larger or higher than the first gate voltage. A voltage of the second voltage supply is higher than a voltage of the first voltage supply.

Short-circuit ruggedness of high-voltage IGBTs

Abstract: The IGBT can run into different short-circuit types (SC I, SC II, SC III). Especially in SC II and III, an interaction between the gate drive unit and the IGBT takes place. A self-turn-off mechanism after short-circuit turn on can occur. Parasitic elements in the connection between the IGBT and the gate unit as well as asymmetrical wiring of devices connected in parallel are of effect to the short-circuit capability. In high-voltage IGBTs, filament formation can occur at short-circuit condition. Destructive measurements with its failure patterns and short-circuit protection methods are shown.

Driving circuit, shifting register, gate driver, array substrate and display device

Abstract: The disclosure relates to the field of liquid crystal display, and provides a driving circuit, a shifting register, a gate driver, an array substrate and a display device. The driving circuit comprises a pull-up module, a first pull-down module, a second pull-down module, a pull-up driving module, a pull-down driving module and a resetting module, wherein the first pull-down module outputs a switching-off signal to the output terminal according to a signal input from the clock retarding signal input terminal and a signal at a pull-down node; a second pull-down module, when the signal input from the signal input terminal is at a low level, outputs a switching-off signal to the pull-up node and the output terminal according to a signal input from a clock signal input terminal; wherein when the signal input from the signal input terminal is at a high level, the signal input from the clock retarding signal input terminal is also at a high level, and the signal input from the clock signal input terminal and that input from the clock retarding signal input terminal are opposite in phase. The driving circuit according to the disclosure can effectively remove the defect of the threshold voltage drifting due to the gate being applied to a bias voltage stress, and can also decrease the noise of the output voltage.

High-speed resonant gate driver with controlled peak gate voltage for silicon carbide MOSFETs

Abstract: Parasitic inductance in the gate path of a Silicon Carbide MOSFET places an upper limit upon the switching speeds achievable from these devices, resulting in unnecessarily high switching losses due to the introduction of damping resistance into the gate path. A method to reduce switching losses is proposed, using a resonant gate driver to absorb parasitic inductance in the gate path, enabling the gate resistor to be removed. The gate voltage is maintained at the desired level using a feedback loop. Experimental results for a 1200 V Silicon Carbide MOSFET gate driver are presented, demonstrating switching loss of 230 µJ at 800 V, 10 A. This represents a 20% reduction in switching losses in comparison to conventional gate drive methods.

An Efficient Resonant Gate-Drive Scheme for High-Frequency Applications

Abstract: Silicon carbide (SiC) and gallium nitride (GaN) devices have been found to withstand high voltages without showing degradation and can be switched at high frequencies, making them attractive for high-power drives. Although Sic/GaN devices can be operated at high temperature and high frequencies, it is important to develop gate-drive circuits to efficiently turn on and off these devices at high speeds. This paper proposes a resonant gate-drive circuit that aims at reducing the power loss associated with high-frequency switching of power insulated gate bipolar transistors/metal–oxide–semiconductor field-effect transistors. The main thrust of the circuit is its application to the motor-drive industry. The proposed circuit is compared with traditional gate-drive circuits from the points of view of power consumption and switching speed. Experimental results are given to illustrate the concept. Test results show that the power consumption using the proposed circuit reduces by a factor of greater than 5 compared with a traditional gate-drive circuit.

Shifting register, gate driver and display device

Abstract: The utility model relates to the technical field of display devices and provides a shift register, a gate driver and a display device. The shift register comprises a pull-up transistor, a drop-down transistor, an output transistor and a reset unit, and further comprises an output drop-down unit and a control transistor. The output drop-down unit is used for electric discharge to an output end, is respectively connected with a current drop-down node, an adjacent-level drop-down node, a low voltage signal end and the output end, and conducts the output end to the low voltage signal end when the current drop-down node or the adjacent-level drop-down node is in high potential. Gate electrode of the control transistor is connected with a pull-up node, drain electrode of the control transistor is connected with the adjacent-level drop-down node, and source electrode of the control transistor is connected with the low voltage signal end. Noise in odd-numbered time units and even-numbered time units after a current output is restrained by the output drop-down unit, generation of multi-output phenomenon is effectively avoided, the stability of Gate Driver on Array (GOA) unit is enhanced, and display effect of a liquid crystal display panel is guaranteed.

Voltage-boosting converters with hybrid energy pumping

Abstract: Voltage-boosting converters with hybrid energy pumping are presented. Hence, the corresponding voltage conversion ratios are higher than the traditional boost converter or some existing voltage-boosting converters. Above all, by changing the circuit connection or turn-on types of switches, there are three voltage conversion ratios to be generated. Hence, there are three types of voltage-boosting converters to be presented herein. Furthermore, for any type, no isolated gate driver is needed instead of one half-bridge gate driver and one low-side gate driver, and the voltage stress on the low-side switch to magnetise the inductor and the voltage stress on the output diode can be reduced as compared to the traditional boost converter. In addition, the basic operating principles of these converters are easy to describe and analyse along with mathematical deductions.

Implementation of an a-Si:H TFT Gate Driver Using a Five-Transistor Integrated Approach

Abstract: An integrated five-transistor/one-capacitor approach for realizing a a-Si:H thin-film transistor (TFT) gate driver operating in multiphase-clock mode is proposed and investigated. The driver needs only one large-size TFT and one small-size storage capacitor. The performance and function of the proposed driver are verified experimentally. The dependence of the performance on the device size is studied in detail. Stability of the fabricated drivers is tested using a flexible measurement scheme. Measured results show that the fabricated gate driver can work stably even though the low-level-holding TFTs have a threshold-voltage shift of 19 V.

Gate driver on array, shifting regester and display screen

Abstract: The embodiment of the present disclosure relates to a technical field of liquid crystal display, and particularly, to a gate driver on array, a shifting register and a display screen. The gate driver on array comprises: a first TFT, a second TFT, a third TFT, a fourth TFT, a capacitor and a pulling-down module, the pulling-down module is connected among a first clock signal input terminal, a second clock signal input terminal, a first node and an output terminal, and is connected with a low voltage signal terminal, for maintaining the first node and the output terminal being in a low level during a non-operation period of the gate driver on array. Thus, the gate driver on array may achieve a bidirectional scan by designing the functions of the input terminal and the reset terminal in the gate driver on array as being implemented symmetrically, without changing a charging-discharging characteristic of nodes, which ensures a reliability and stabilization of the circuit.

Display and touch panels with drive and sense techniques

Abstract: The present invention provides a display device comprising: a display panel including a data line, a gate line, and a pixel; a data driver configured to output a data signal to the data line; a gate driver configured to output a gate signal to the gate line; and a signal controller configured to control the data driver, and the gate driver, wherein at least one of the data driver and the gate driver comprises a first current monitoring unit configured to monitor output current of the at least one of the data driver and the gate driver.

Highly Reliable Integrated Gate Driver Circuit for Large TFT-LCD Applications

Abstract: This letter presents a novel integrated hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) gate driver circuit using ac driving (33% duty) to prevent the floating of row lines and reduce the bias voltage of pull-down TFTs to suppress the threshold voltage (VTH) shift of a-Si:H TFTs. The VTH shift of the TFTs in this design is reduced by 49.93% from that achieved using the 25%-duty ac-driving structure. In a reliability test, the new circuit operates stably at a high temperature (T = 60°C) for more than 240 h.