Showing papers on "Logic level published in 2013"

Endurance and retention flash controller with programmable binary-levels-per-cell bits identifying pages or blocks as having triple, multi, or single-level flash-memory cells

Abstract: An retention flash controller reads assigned-level bits from a bad block/erase count table or from a page status table that indicate when flash memory cells operate as Triple-Level-Cell (TLC), Multi-Level-Cell (MLC), or Single-Level-Cell (SLC). Pages that fail as TLC or MLC are downgraded for use as SLC pages by changing the assigned-level bits. The level bits adjust truth tables used by translation logic that receives inputs from voltage comparators reading a bit line. The range of voltages for each logic level may be adjusted by the truth tables or by programmable registers. The programming voltage or programming pulses may be adjusted to increase endurance and the number of permitted program-erase cycles while reducing retention times before a refresh is needed of the flash cells. Mixed configurations of flash memory have MLC blocks and MLC as SLC blocks, or other combinations.

Implication logic gates using spin-transfer-torque-operated magnetic tunnel junctions for intrinsic logic-in-memory

Abstract: As the feature size of CMOS components scales down, the standby power losses due to high leakage currents have become a top concern for modern circuit design. Introducing non-volatility in logic circuits allows to overcome the standby power issue. Magnetic tunnel junctions (MTJs) offer a great potential, because of their non-volatility, unlimited endurance, CMOS compatibility, and fast switching speed. This work proposes current- and voltage-controlled MTJ-based implication (IMP) logic gtes for future non-volatile logic-in-memory architecture. The MTJ-based implication logic realizes an intrinsic logic-in-memory known as “stateful” logic for which the MTJ devices serve simultaneously as memory elements and logic gates. Spintronic implication logic gates are analyzed by using a SPICE model for spin-transfer torque (STT) MTJs in order to show the reliability of the IMP operation. It has been demonstrated that the proposed current-controlled implication gate offers a higher performance (power and reliability) than the conventional voltage-controlled one. The realization of the spintronic stateful logic operations extends non-volatile electronics from memory to logical computing applications and opens the door for more complex logic functions to be realized with MTJ-based devices. We present a stateful logic circuit based on the common STT-MRAM architecture capable of performing material implication. As an application example, an IMP-based implementation of a full-adder is presented.

A Digital Frequency-Locked Loop System for Capacitance Measurement

Abstract: Similar to phase-locked loops, frequency-locked loops (FLLs) are useful in many applications involving waveform synchronization or synthesis. Simple logic circuit-based relaxation oscillators convert capacitance to frequency, which is a characteristic inverse relationship between output frequency and input capacitance. The oscillator's logic level square-wave output can be fed into an all-digital FLL that will frequency lock to the input signal and produce a digital output word N, where N is inversely proportional to the input frequency. The result is that N is linearly proportional to the unknown capacitance in the oscillator. This novel approach allows a simple FFL implementation for capacitance measurement and is demonstrated in hardware using a capacitive sensor that measures the mass of small quantities of water with an output capacitance range of 75-185 pF.

Constant Delay Logic Style

Abstract: A constant delay (CD) logic style is proposed in this paper, targeting at full-custom high-speed applications. The CD characteristic of this logic style regardless of the logic type makes it suitable in implementing complicated logic expressions such as addition. CD logic exhibits a unique characteristic where the output is pre-evaluated before the inputs from the preceding stage is ready. This feature offers performance advantage over static and dynamic domino logic styles in a single-cycle multistage circuit block. Several design considerations including timing window width adjustment and clock distribution are discussed. Using 65-nm general-purpose CMOS technology, the proposed logic demonstrates an average speedup of 94% and 56% over static and dynamic domino logic, respectively, in five different logic gates. Simulation results of 8-bit ripple carry adders show that CD logic is 39% and 23% faster than the static and dynamic-based adders, respectively. CD logic also demonstrates 39% speedup and 64% (22%) energy-delay product (EDP) reduction from static logic at 100% (10%) data activity in 32-bit carry lookahead adders. For 8-bit Wallace tree multiplier, CD logic achieves a similar speedup with at least 50% EDP reduction across all data activities.

BDS-MAJ: a BDD-based logic synthesis tool exploiting majority logic decomposition

Abstract: Despite the impressive advance of logic synthesis during the past decades, a general methodology capable of efficiently synthesizing both control and datapath logic is still missing. Indeed, while synthesis techniques for random control logic (AND/OR-intensive) are well established, no dominant method for automated synthesis of datapath logic (XOR/MAJ-intensive) has yet emerged. Recently, Binary Decision Diagrams (BDDs) have been adopted to create an optimization system, named BDS, that supports integrated synthesis of both AND/OR- and XOR-intensive functions through functional logic decomposition on the BDD structure. However, it does not support direct decomposition and manipulation of majority logic which, instead, is widely used in datapath circuits. In this paper, we present the first BDD-based majority logic decomposition method and a logic decomposition system, BDS-MAJ, that enables efficient logic synthesis for both random control and datapath circuits. Experimental results show that logic synthesis based on BDS-MAJ produces CMOS circuits having on average 28.8% and 26.4% less area and, at the same time, 12.8% and 20.9% smaller delay with respect to academic ABC and BDS synthesis tools. Compared to commercial Synopsys Design Compiler synthesis tool, BDS-MAJ reduces on average the circuit area by 6.0% and decreases the delay by 7.8%.

Noise-Aided Logic in an Electronic Analog of Synthetic Genetic Networks

Abstract: We report the experimental verification of noise-enhanced logic behaviour in an electronic analog of a synthetic genetic network, composed of two repressors and two constitutive promoters. We observe good agreement between circuit measurements and numerical prediction, with the circuit allowing for robust logic operations in an optimal window of noise. Namely, the input-output characteristics of a logic gate is reproduced faithfully under moderate noise, which is a manifestation of the phenomenon known as Logical Stochastic Resonance. The two dynamical variables in the system yield complementary logic behaviour simultaneously. The system is easily morphed from AND/NAND to OR/NOR logic.

Low-density parity-check decoder disparity preprocessing

Abstract: Described embodiments provide a media controller that performs error correction on data read from a solid-state media. The media controller receives a read operation from a host device to read one or more given read units of the solid-state media. The media controller reads the data for the corresponding read units from the solid-state media employing initial values for one or more read threshold voltages. Only if a disparity between an actual number of bits at a given logic level included in the read data and an expected number of bits at the given logic level included in the read data has not reached a predetermined threshold, the media controller decodes the read data and provides the decoded data to the host device.

Low Cost Concurrent Error Masking Using Approximate Logic Circuits

Abstract: With technology scaling, logical errors arising due to single-event upsets and timing errors arising due to dynamic variability effects are increasing in logic circuits. Existing techniques for online resilience to logical and timing errors are limited to detection of errors, and often result in significant performance penalty and high area/power overhead. This paper proposes approximate logic circuits as a design approach for low cost concurrent error masking. An approximate logic circuit predicts the value of the outputs of a given logic circuit for a specified portion of the input space, and can indicate uncertainty about the outputs over the rest of the input space. Using portions of the input space that are most vulnerable to errors as the specified input space, we show that approximate logic circuits can be used to provide low overhead concurrent error masking support for a given logic circuit. We describe efficient algorithms for synthesizing approximate circuits for concurrent error masking of logical and timing errors. Results indicate that concurrent error masking based on approximate logic circuits can mask 88% of targeted logical errors for 34% area overhead and 17% power overhead, 100% timing errors on all timing paths within 10% of the critical path delay for 23% area overhead and 8% power overhead, and 100% timing errors on all timing paths within 20% of the critical path delay for 42% area overhead and 26% power overhead.

Low Complexity Out-of-Order Issue Logic Using Static Circuits

Abstract: In this paper a single-cycle issue queue circuit architecture that simplifies the wakeup and selection logic is proposed. The micro-architecture and fully static CMOS circuits are presented for a 32-entry queue that issues four instructions per cycle. The instruction-ready signals are divided into groups and processed in parallel to issue the four oldest ready instructions. The complete issue queue and prioritization logic requires 20 inversions, allowing simulated circuit operation at over 4 GHz in a foundry 45 nm SOI fabrication process.

A fast and energy-efficient level shifter with wide shifting range from sub-threshold up to I/O voltage

Abstract: This paper presents a fast and energy-efficient current mirror based level shifter with wide shifting range from sub-threshold voltage up to I/O voltage. Small delay and low power consumption are achieved by addressing the non-full output swing and charge sharing issues in the level shifter from [4]. The measurement results show that the proposed level shifter can convert from 0.21V up to 3.3V with significantly improved delay and power consumption over the existing level shifters. Compared with [4], the maximum reduction of delay, switching energy and leakage power are 3X, 19X, 29X respectively when converting 0.3V to a higher voltage between 0.6V and 3.3V.

Nanomagnetic Logic Microprocessor: Hierarchical Power Model

Abstract: The interest in emerging nanotechnologies has been recently focused on nanomagnetic logic (NML), which has unique appealing features. NML circuits have very low power consumption and, because of their magnetic nature, maintain the information safely stored even without power supply. The nature of these circuits is much different from that of CMOS circuits. As a consequence, to better understand NML logic, complex circuits and not only simple gates must be designed. This constraint calls for a new design and simulation methodology. It should efficiently encompass manifold properties: 1) being based on commonly used hardware description language (HDL) in order to easily manage complexity and hierarchy; 2) maintaining a clear link with physical characteristics; and 3) modeling performance aspects such as speed and power, together with logic behavior. In this paper, we present a very-high-speed integrated circuits HDL (VHDL) behavioral model for NML circuits, which allows the evaluation of not only the logic behavior but also its power dissipation. It is based on a technological solution called “snake-clock.” We demonstrate this model using a case study which offers the right variety of internal substructures to test the method: a 4-bit microprocessor designed using asynchronous logic. The model enables a hierarchical bottom-up evaluation of the processor logic behavior, area, and power dissipation, which we evaluate using a benchmark division algorithm. The results highlight the flexibility and the efficiency of this model, as well as the remarkable improvements that it brings to the analysis of NML circuits.

Reliability Analysis and Comparison of Implication and Reprogrammable Logic Gates in Magnetic Tunnel Junction Logic Circuits

Abstract: Non-volatile logic is a promising solution to overcome the leakage power issue which has become an important obstacle to scaling of CMOS technology. Magnetic tunnel junction (MTJ)-based logic has a great potential, because of the non-volatility, unlimited endurance, CMOS compatibility, and fast switching speed of the MTJ devices. Recently, by direct communication between spin-transfer-torque-operated MTJs, several realizations of intrinsic logic-in-memory circuits have been demonstrated for which the MTJ devices are used simultaneously as memory and computing elements. Here, we present a reliability analysis of the MTJ-based logic operations and show that the reliability is an essential prerequisite of these MTJ-based logic circuits. It is demonstrated that for given MTJ device characteristics, the implication logic architecture, a new kind of logic based on material implication, significantly improves the reliability of the MTJ-based logic as compared to the reprogrammable logic architecture which is based on the conventional Boolean logic operations AND, OR, etc. Implementing the implication gates in spin-transfer torque magnetic random access memory arrays provides pure electrical read/write and logic operations and also allows fan-out to multiple outputs.

Energy efficient code converters using reversible logic gates

Abstract: In this technological world development in the field of nanometer technology leads to minimize the power consumption of logic circuits. Reversible logic design has been one of the promising technologies gaining greater interest due to less dissipation of heat and low power consumption. In digital systems code conversion is a widely used process for reasons such as enhancing security of data, reducing the complexity of arithmetic operations and thereby reducing the hardware required, dropping the level of switching activity leading to more speed of operation and power saving etc. This paper proposes novel Reversible logic design for code conversion such as Binary to Gray code, Gray to Binary code, BCD to Excess 3 code, Excess 3 to BCD code.

DPA resistance of charge-sharing symmetric adiabatic logic

Abstract: We investigate our previously proposed charge sharing symmetric adiabatic logic, which was designed to thwart differential power analysis (DPA) attack. The ability of the logic to withstand DPA attacks is analyzed from the variations in the transitional power consumption of individual logics and in the bit-parallel cellular multiplier over GF(2m). Then, we compare the results with those of the previous secure logic styles using the same parameters and under the same conditions. Based on the simulated program with integrated circuit emphasis (SPICE) simulation results, we deduce that our proposed logic is a suitable candidate for secure hardware application in the low-power and low-frequency fields, such as contactless smart card, RFID tags, and wireless sensors.

Modified gdi technique - a power efficient method for digital circuit design

Abstract: This paper presents logic style comparisons based on different logic functions and claimed modified Gate Diffusion Input logic (Mod-GDI) to be much more power-efficient than Gate Diffusion Input logic (GDI) and complementary CMOS logic design. However, DC and Transient analysis performed on more efficient modified Gate Diffusion Input logic (Mod-GDI) circuit realizations and a wider range of different logic cells, as well as the use of practical circuit arrangements reveal Mod-GDI to be superior to GDI and CMOS in the majority cases with respect to speed, area, power dissipation, and power-delay products. This manuscript shows that Mod-GDI is the logic style of preference for the realization of arbitrary combinational circuits, if low voltage, low power, and small power-delay products are of concern. All Simulations are performed through PSPICE based on 0.18μm CMOS technology, and results show power characteristics of Mod-GDI technique of low power digital circuit design. Simulation results shows up to 45% reduction in power-delay product in Mod-GDI. Mod-GDI approach allows realization of a broad variety of multifaceted logic functions by means of only two transistors. This technique is appropriate for designing of fast, low power circuits, using reduced number of transistor (as compared to CMOS techniques), while improving power characteristics.

Method for Managing the Operation of a Circuit Connected to a Two-Wire Bus

Abstract: A method is provided for managing the operation of a circuit operating in a slave mode. The circuit is connected to a bus having at least two of wires and a priority logic level. The slave circuit imposes the priority logic level on a first wire of the bus. While imposing, the slave circuit detects a possible conflict on the first wire resulting from a forcing, external to the slave circuit, of the first wire to another logic level. Upon detecting a conflict, the slave circuit is placed in a state stopping the sending by the circuit of any data over the bus while leaving the circuit listening to the bus.

Probabilistic Modeling during Power Estimation for Mixed Polarity Reed-Muller Logic Circuits

Abstract: Expressing logic functions in terms of Reed-Muller expansions is preferred in some communication circuits for its certain advantages like lower power dissipation. This paper presents a power estimation model for Mixed Polarity Reed-Muller (MPRM) logic circuits from a probabilistic point of view. It is mainly used in combinational circuits under the zero-delay hypothesis. A key feature of this technique is that it provides an accurate and efficient way to handle temporal signal correlations during estimation of average power by using lag-one Markov chains. Besides, an ordered binary-decision diagram (OBDD) based procedure is used to propagate the temporal correlations from the primary inputs throughout the network. This model has been evaluated in the C language and a comparative analysis has been presented for many benchmark circuits. The results show that this model gives very good accuracy and does well in low power design for MPRM logic circuits.

Capacitive level shifter devices, methods and systems

Abstract: Systems and methods of use relate to a circuit that is designed to detect the state of two control signals, wherein one control signal indicates an ON state for the gate driver and the other control signal indicates an OFF state for the gate driver. The circuit responds to each of the control signals by controlling the gate driver so that it drives an output either high or low. The circuit can also be configured to control the gate driver so that it to drives the output (either high or low) when neither control signal is present.

Simple Noise Margin Model for Optimal Design of Unipolar Thin-Film Transistor Logic Circuits

Abstract: The noise margin (NM) of an inverter is an important feature for the operation stability of the digital circuits. Owing to their simple structure, easy processes, and relatively high gain, the unipolar zero-VGS-load logic design is widely used for implementation of digital circuits in various thin-film transistor (TFT) technologies. In this paper, a simple NM model clarifying the relationship between the NM and electrical/device parameters is developed for the zero-VGS-load inverter. The model is verified by circuit simulations, and is capable of providing a useful guideline for optimal design of unipolar TFT logic circuits. Finally, the application of the derived model in a static random access memory cell design is discussed.

Level shifter circuit and operation method thereof

Abstract: A level shifter transfers a first voltage signal to a second voltage signal. The level shifter comprises a comparison circuit, a delay circuit, and a selection circuit. The comparison circuit generates a first signal according to the comparison result between the first voltage signal and the reverse-phase signal of the first voltage signal. The delay circuit generates a second signal according to the first voltage signal. The selection circuit receives the first and the second signals and chooses the higher voltage one from the first signal and the second signal to be the second voltage signal.

Robust secure charge-sharing symmetric adiabatic logic against side-channel attacks

Abstract: This paper implements our proposed charge-sharing symmetric adiabatic logic (CSSAL) into the cellular multiplier used in finite field over GF(2m) arithmetic using secure system for resistant against side-channel attacks. To validate our proposed logic, we have evaluated the current traces and energy dissipation of the individual secure adiabatic logics; proposed CSSAL, secure adiabatic logic, symmetric adiabatic logic, 2N-2N2P, and the conventional three-phase dual-rail pre-charged logic. Furthermore, the thoroughly investigation and comparative study on the logic's resistance and the energy efficiency in the multiplier over GF(2m) have been conducted. Based on the obtained SPICE simulation results, we deduce that, the proposed typical logics is stronger against differential power analysis and more robust for differential electromagnetic analysis attacks, because it consumes constant low power and uniformly low peak current since ever in the literature.

High speed level shifter for converting low input voltage into wide-range high output voltage

Abstract: A high speed level shifter is provided for converting a low input voltage into a wide-range high output voltage. By utilizing two switching units to improve the latching speed of the latching unit of the level shifter, the duty cycle of the input signal is nearly equal to the duty cycle of the output signal.

Device–Circuit Co-design for Beyond 1 GHz 5 V Level Shifter Using DeMOS Transistors

Abstract: This paper presents a device-circuit co-design approach to achieve a low swing, high speed 1.2-5 V level shifter (LS) using drain extended MOS (DeMOS) transistors for system on chip applications in advance CMOS technologies. Limiting factors of the high-voltage devices during transients are identified and accordingly it is shown that the maximum operating frequency of traditional LS can be increased by at least a factor of two. It is demonstrated that optimization of key device parameters of the DeMOS transistor enhances the maximum clock frequency to more than 1 GHz while preserving the device breakdown voltage and duty cycle of the level shifted signal.

Apparatus and method for writing data to memory array circuits

Abstract: A write driver for a memory circuit includes a control circuit configured to: operate a first push-pull driver to generate a first drive signal in a first voltage domain at a first node based on an input signal in a second domain and in response to a mode select signal being in a first mode, wherein the first drive signal is at a same logic level as the input signal; operate a second push-pull driver to generate a second drive signal in the first voltage domain at a second node based on the input signal and in response to the mode select signal being in the first mode, wherein the second drive signal is at a complement logic level with respect to the input signal; and operate the first and second push-pull drivers to float the first and second nodes in response to the mode select signal being in a second mode.

A Review on Energy Efficient CMOS Digital Logic

Abstract: Autonomy of power supply used in portable devices directly depends on energy efficiency of digital logic. This means that digital systems, beside high processing power and very complex functionality, must also have very low power consumption. Power consumption depends on many factors: system architecture, technology, basic cells topology-speed, and accuracy of assigned tasks. In this paper, a review and comparison of CMOS topologies techniques and operating modes is given, as CMOS technology is expected to be the optimum choice in the near future. It is shown that there is a full analogy in the behavior of digital circuits in sub-threshold and strong inversion. Therefore, synthesis of digital circuits is the same for both strong and weak operating modes. Analysis of the influence of the technology, MOS transistor threshold voltage ( V t ) and power supply voltage ( V dd ) on digital circuit power consumption and speed for both operating modes is given. It is shown that optimal power consumption (minimum power consumption for given speed) depends on optimal choice of threshold, and power supply voltage. Multi V dd /V t techniques are analyzed as well. A review and analysis of alternative logical circuit's topologies – pass logic (PL), complementary pass logic (CPL), push-pull pass logic (PPL) and adiabatic logic – is also given. As shown, adiabatic logic is the optimum choice regarding energy efficiency.

Voltage level shifter

Abstract: The voltage level shifter includes a first voltage shift circuit, a second voltage shift circuit, a first switch circuit, a second switch circuit, a third switch circuit and a fourth switch circuit. The first voltage shift circuit receives a first input voltage, and the second voltage shift circuit receives a second voltage shift circuit. When the first voltage is high level voltage, a second output voltage and a first voltage are transformed to a ground voltage so as to open the second switch circuit and the fourth switch circuit, and then the first output voltage is transited to a system voltage. When the second voltage is high level voltage, a first output voltage and a second voltage are transited to a ground voltage so as to open the first switch circuit and the third switch circuit, and then the second output voltage is transited to the system voltage.

A Low-Power DCVSL-Like GIDL-Free Voltage Driver for Low-Cost RFID Nonvolatile Memory

Abstract: The realization of a low-cost passive radio frequency identification (RFID) tag requires the ability to fabricate the system in a bulk CMOS process without any additional process steps. A recently presented single-poly C-Flash memory bitcell provides an ultralow-power option for implementation of a nonvolatile memory array for use in an RFID system, using only core masks. This cell requires the application of a 10-V potential difference between the cell's control lines for program and erase operations. Providing the required voltages, while using only standard devices results in several design challenges for the voltage drivers, such as the elimination of gate-induced drain leakage (GIDL) currents. In this paper, we present a pair of voltage driver architectures that utilize novel techniques to overcome these challenges. In addition, for the first time, we present an in-depth analysis of the dynamic behavior of standard level shifters. This analysis is applied to our proposed GIDL-free level shifters to provide a sizing methodology for optimization of the area, energy-per-operation, and delay of these circuits. The drivers were designed and fabricated in a TowerJazz 0.18- μm bulk CMOS technology, providing the required functionality with a low static-power figure of 47-49 pW and 0.03-0.36 pJ energy-per-operation.

Power supply device, and vehicle-mounted apparatus and vehicle using same

Abstract: A power supply device includes: a comparator that compares an error voltage and a slope voltage to generate a comparison signal; a PWM pulse generation portion that generates a PWM pulse based on a clock signal and the comparison signal; an on-time fixed pulse generation portion that uses the comparison signal as a trigger to generate an on-time fixed pulse where an on-time and an on-time number are constant; a selector that selects any one of the PWM pulse and the on-time fixed pulse; and a selector control portion that generates a selector control signal such that any one of the PWM pulse and the on-time fixed pulse is selected according to whether or not the comparison signal is kept at the same logic level over a predetermined mask period

Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37V 980kHz near-threshold logic circuits

Abstract: In order to improve the energy efficiency of logic circuits, reductions in capacitance (C) and power supply voltage (VDD) are required, as energy consumption is proportional to CVDD2. Near-threshold (Vt) operation achieves an energy minimum. Resonant clocking can reduce the effective capacitance of the clock distribution network. In this work, a new resonant clocking scheme enabling power reduction at any clock frequency is proposed and applied to a 0.37V 980kHz near-Vt logic circuit in 40nm CMOS.