Showing papers on "MOSFET published in 1982"

An analytical breakdown model for short-channel MOSFET's

Abstract: Avalanche-induced breakdown mechanisms for short-channel MOSFET's are discussed. A simple analytical model that combines the effects due to the ohmic drop caused by the substrate current and the positive feedback effect of the substrate lateral bipolar transistor is proposed. It is shown that two conditions must be satisfied before breakdown will occur. One is the emission of minority carriers into the substrate from the source junction, the other is sufficient avalanche multiplication to cause significant positive feedback. Analytical theory has been developed with the use of a published model for short-channel MOSFET's. The calculated breakdown characteristics agree well with experiments for a wide range of processing parameters and geometries.

Submicrometer MOSFET structure for minimizing hot-carrier generation

Abstract: This paper reports on investigation of channel hot-carrier generation for various device structures. The dependences of channel hot-carrier generation on MOSFET structure are characterized by measuring the gate current and the substrate current as low as on the order of 10-15A. The measured gate current due to hot-electron injection into the oxide is modeled numerically as thermionic emission from heated electron gas over the Si-SiO 2 energy barrier. The substrate current due to hot-hole injection into the substrate is also modeled analytically. On the basis of the experiments and analyses, two device structures are proposed for minimizing hot-carrier generation and associated problems in submicrometer MOSFET: a graded drain junction structure and an offset gate structure. The proposed device structures provide remarkable improvements, raising by 2 V the highest applicable voltages as limited by hot-electron injection, as well as raising by 1-3 V the drain sustaining voltages as determined by the substrate hot-hole current. The influence of electron-beam radiation on the gate oxide is also discussed in relation to the trapping of hot electrons.

Processes for manufacturing insulated-gate semiconductor devices with integral shorts

Abstract: Process for manufacturing insulated-gate semiconductor devices such as MOSFETs being with a semiconductor wafer (such as silicon) including a drain region, a gate insulating layer initially formed uniformly on the surface of the drain region, and a polysilicon conductive gate layer. A two-stage polysilicon etch procedure is disclosed. The initial etch produces relatively narrow channels with substantially vertical sidewalls. Unetched portions of the polysilicon layer are used as masks during a first P type diffusion to form a shorting extension of the device base region and during the forming of a silicon nitride mask layer by a highly directional process, such as ion implantation, which avoids the formation of any nitride layer on the channel sidewalls. In a subsequent lateral etch step, previously unetched portions of the polysilicon gate electrode layer are etched to define insulated polysilicon gate electrode structures. These structures extend upwardly from and are spaced along the principal surface, and are also spaced from the silicon nitride masks. Then, the silicon nitride masks are each used as a combination diffusion and selective oxidation mask to form MOSFET source and base regions and to oxidize the polysilicon gate electrode sidewalls. The silicon nitride mask is removed, and appropriate electrode metallization applied.

A half micron MOSFET using double implanted LDD

Abstract: Double-implanted LDD, which consists of self-aligned p pockets below the n regions in LDD, is introduced to improve both breakdown and short channel effects. Its fabrication and experimental results are presented. The device optimized for a 0.5µm channel and 3.5V supply is discussed.

Small-signal MOSFET models for analog circuit design

Abstract: Presents first-order large-signal MOSFET models and derives corresponding small-signal models. The parameters of the small-signal models are related to operating-point bias and to the parameters of the IC process used to fabricate the device. The impact upon small-signal performance of many second-order effects present in small-geometry MOSFETs is explored. A representative analog circuit, fabricated with a 1 /spl mu/m feature-size NMOS technology, is analyzed using the small-signal models derived. Results of approximate analysis, without the use of computer aids, are compared with detailed computer simulation results.

A simple and accurate method to measure the threshold voltage of an enhancement-mode MOSFET

Abstract: A new, simple method to measure the V T of an enhancement-mode MOSFET has been developed based on the analytical model of the subthreshold current. V T is determined to be the gate voltage at which the I DS reaches the constant threshold current, and this method is accurate over a wide range of device dimensions, bias conditions, and operating temperatures.

Speed limitations due to interconnect time constants in VLSI integrated circuits

Abstract: The RC time constants for various interconnect materials, including poly-Si, silicides, and Al, are compared with MOSFET speeds at near-micron and submicron design rules. It is found that for design rules below ∼ 2 µm, the rise time of Al interconnects one cm long can exceed the switching delay of state-of-the-art MOSFET circuits. This speed limitation becomes more severe as design rules are reduced further. The effects of the sheet resistance and thickness of gate level interconnects, the thickness of the field oxide, and the dielectric constant of the insulating overlays are quantified.

SPICE Modeling for Small Geometry MOSFET Circuits

Abstract: VLSI circuit simulation requires computationally efficient MOSFET models. In this paper, VLSI circuit simulator models for the active device and some important passive devices are described. A quasi-physical short channel MOSFET current model is derived. This current model contains both above-threshold and subthreshold components. The values of the model parameter are extracted automatically from measured I-V data. The reduction in process information in this representation is shown to be tolerable using a proper quantization of the geometry and device type space. Narrow width effect is also included. A charge conserving MOSFET capacitor model is also given. The importance of the parasitic devices on VLSI circuit is shown and a model for the fringing capacitance due to finite gate thickness is introduced. A "process box" based on the statistical variation of parameters is extracted from a completely automated device characterization system. Experimental results indicate that the width and length are independent random variables. This statistical information allows the circuit response to be simulated across the process window.

Generation of interface states by hot hole injection in MOSFET's

Abstract: The emission of hot electrons and hot holes from n-channel MOSFET's into the gate oxide is investigated as a function of the gate bias for a given lateral electric field. The resulting electron gate current as well as the substrate current are analyzed for both the saturation and the linear regime of the transistor. In the saturation regime, a remarkable increase of interface states occurs which can be correlated with the hole generation due to avalanche multiplication in the high-field region. In this case, the electric field normal to the Si-SiO 2 interface near the drain aids in the injection of hot holes along the channel which initiates acceptor-type interface states. In the linear operation regime, however, no pronounced generation of interface states can be detected.

Submicrometer MOSFET Structure for Minimizing Hot-Carrier Generation

Abstract: This paper reports on investigation of channel hot-carrier generation for various device structures The dependence of channel hot-carrier generation on MOSFET structure are characterized by measuring the gate current and the substrate current as low as on the order of 10/sup -15/ A The measured gate current due to hot-electron injection into the oxide is modeled numerically as thermionic emission from heated electron gas over the Si-SiO/sub 2/ energy barrier The substrate current due to hot-hole injection into the substrate is also modeled analytically On the basis of the experiments and analyses, two device structures are proposed for minimizing hot-carrier generation and associated problems in submicrometer MOSFET: a graded drain junction structure and an offset gate structure The proposed device structures provide remarkable improvements, raising by 2 V the highest applicable voltages as limited by hot-electron injection, as well as raising by 1-3 V the drain sustaining voltages as determined by the substrate hot-hole current The influence of electron-beam radiation on the gate oxide is also discussed in relation to the trapping of hot electrons

Impact ionization at very low voltages in silicon

Abstract: Impact ionization in germanium and silicon has been the subject of extensive theoretical and experimental work. The general agreement in the literature for the value of the threshold energy for impact ionization is 1.5 times the energy gap (EG) at room temperature which corresponds to 1.65 eV in the case of silicon. In this work, using a metal semiconductor field effect transistor (MOS device), as a sensitive tool for detecting small multiplication currents, impact ionization is investigated in a region where the total potential drop over which carriers are accelerated is less than the threshold energy for impact ionization. Impact ionization currents are detected for potential drop as low as 1.1 V. The positive temperature coefficient in this region suggests that the initial thermal distribution of the electrons dominates impact ionization for very low accelerating voltages.

Complementary MOSFET logic circuit

Abstract: Disclosed is a complementary MOSFET logic circuit having a complementary MOS inverter (23) with a pregiven ratio of the channel widths of a P channel MOSFET (211 and an N channel MOSFET (22) and pregiven threshold voltages of the FETs (21, 22) so as to have an input voltage characteristic adapted for an output voltage characteristic, and a buffer circuit (24) with such an arrangement that a bipolar transistor (25) for receiving at the base a signal at the output terminal of said complementary MOS inverter (23) and an N channel MOSFET (26) for receiving at the gate an input signal applied to the complementary MOS inverter (23) are connected in series between a high potential applying point and a low potential applying point, and a signal corresponding to a logic output signal of the complementary MOS inverter (23) is produced ot the output terminal thereof.

Power MOSFET temperature measurements

Abstract: Three temperature-sensitive electrical parameters are compared as thermometers for power MOSFET devices. The parameters are the forward drain-body diode voltage, the source-gate voltage, and the on-resistance. The results are also compared with temperatures measured with an infrared microradiometer. The procedure, apparatus, and circuits required to use each of the parameters as a thermometer are described. Some general considerations for measuring the temperature of power semiconductor devices are also discussed. Each parameter is found to be satisfactory for measuring the temperature of power MOSFETs. The sourcegate voltage measures a temperature nearest to the peak device temperature, and the drain-body diode voltage shows the least variation in calbiration from device to device.

Solid state relay circuit employing MOSFET power switching devices

Abstract: A solid state relay employing MOSFET power switching devices is disclosed A d-c output relay is disclosed using a single power MOSFET device and an a-c output relay is disclosed employing series opposition power MOSFETS

1.25 /spl mu/m Deep-Groove-Isolated Self-Aligned Bipolar Circuits

Abstract: This paper concerns the design and characteristics of the high-performance bipolar switching devices and circuits for digital applications at lithographic dimensions of about 1 /spl mu/m. The impurity profile of the transistors is optimized for speed while maintaining sufficient current gain and punchthrough voltage. The circuits were fabricated on epitaxial wafers of a 0.5 /spl mu/m flat zone in an advanced bipolar technology featuring self-aligned polysilicon base and emitter contacts, deep-groove device isolation, and electron beam lithography. The experimental results show that n-p-n transistors exhibit a current gain greater than 40 at current densities as high as 1.3 mA//spl mu/m/sup 2/. As a result of reduced line width and polysilicon contacts, the current gain of Iateral epi-base p-n-p transistors is greater than 20 at low-current levels and remains greater than 1 at a current density as high as 0.12 mA//spl mu/m emitter edge. ECL (FI = FO = 1) circuits show a gate delay as low as 114 pS at a power dissipation of 4.9 mW. High-density I/sup 2/L/MTL circuits (average FI = 2, FO = 2.5, C/sub w/ = 90 fF) show delay of 0.91 ns at 0.17 mW. These results demonstrate that the present bipolar technology provides not only high-speed circuits, but also circuits for VLSI applications with density comparable to MOSFET.

Unpowered fast gate turn-off FET

Abstract: A fast turn-off MOSFET circuit is provided by a JFET in the gate circuit of the MOSFET which is connected to the same gate drive terminal as the MOSFET. The JFET becomes conductive upon turn-off of the MOSFET due to removal of gate drive. Conduction of the JFET provides faster discharge therethrough of residual stored charge on the MOSFET gate, whereby to facilitate faster MOSFET turn-off. A zener diode is connected in the gating circuitry and has a greater breakover voltage than the pinch-off voltage of the JFET, such that during turn-on, gate drive first pinches OFF the JFET and then charges up the MOSFET gate to drive the MOSFET into conduction.

Direct-write metallization of Silicon MOSFET's using laser photodeposition

Abstract: Gate electrodes of enhancement-mode silicon MOSFET's have been written directly using a new, mask-free laser photodeposition technique. Transistor transconductances and threshold voltages were systematically tuned by varying the gate geometry with the laser beam. The new metallization process is potentially useful for tuning and optimizing the characteristics of individual devices in integrated circuits.

Mobility degradation due to the gate field in the inversion layer of MOSFET's

Abstract: A simple classical theory that explains how the carrier mobility degrades as a function of the gate field in the inversion layer of MOSFET's is presented here. A formula of effective gate field-dependent mobility is derived and is reducible to the well-known empirical formula at the limit of large gate oxide thickness. However, their difference becomes drastic at thin gate oxide and high gate fields. For example, at t_{ox} = 200 A, and V_{GS} = 5 V, the difference is about 20% for mobility prediction if same physical parameters are used in both formulae. The present theory has been incorporated into a new model for I-V characteristics of MOSFET's and good agreements with experimental data for t_{ox} = 200 A transistors have been observed.

Transient response of n‐channel metal‐oxide‐semiconductor field‐effect transistors during turnon at 10–25 °K

Abstract: The transient, excess source‐drain current which occurs under freeze‐out conditions when a metal‐oxide‐semiconductor field‐effect transistor (MOSFET) is switched into a conducting state is described. The major features of the observed transient response for n‐channel MOSFET’s in the temperature range 10–25 °K are explained in terms of a simple one‐dimensional model. The transient response is largely independent of both temperature (in this range) and the static current level, except for the variation of relaxation rate with temperature. The transient response waveform and the temperature dependence of the relaxation rate for n‐channel MOSFET’s differ greatly from previously reported results on p‐channel MOSFET’s.

An optimally designed process for submicrometer MOSFET's

Abstract: An n-channel MOS process has been optimized to yield desirable characteristics for submicrometer channel-length, MOSFET's. Process/device simulation is extensively used to find an optimized processing sequence compatible with typical production-line processes. The simulation results show an excellent agreement with experimental data. We have obtained long-channel subthreshold characteristics, saturation drain characteristics up to 5 V, and a minimized substrate bias sensitivity for transistors with channel lengths as small as 0.5 µm. The short-channel effects have been also minimized. A new self-aligned silicidation technology has been developed to reduce the increased resistance of diffused layers with down-scaled junction depths.

Total Dose Radiation-Bias Effects in Laser-Recrystallized SOI MOSFET's

Abstract: Laser-recrystallized polysilicon over an insulating layer, such as silicon dioxide, provides a new approach for the fabrication of active devices which are dielectrically isolated from the substrate. This paper deals with initial radiation studies for gamma radiation doses from 1 krad to 1 Mrad(Si) on n- and p-channel MOSFET's fabricated in such laser-recrystallized silicon. The n-channel devices were used to investigate the effect of interfacial charge trapping at both the gate oxide/ and underlying oxide/ recrystallized silicon interface. Data on radiation-induced leakage currents and threshold shifts are presented as a function of radiation dose for worst-case irradiation-bias conditions and for various substrate biases during irradiation. Additionally, the effect of a deep boron implant is presented. Although a hardened process was not used to fabricate the MOSFET's, the results show promise for a radiation-hardened alternative to SOS when logic design allows negative substrate biasing and for a radiation-hardened stacked non-planar three-dimensional circuitry.

Hot-electron induced excess carriers in MOSFET's

Abstract: The existence of minority carriers in the substrate of n-channel MOSFET's operating in the saturation region is shown to be induced by turn-on of the source-substrate junction and photon generation. The two mechanisms are demonstrated experimentally and the photon-generation mechanism is further illustrated on a p-well CMOS wafer. Photon generation poses a constraint in VLSI dynamic RAM design.

Threshold-voltage instability of n-channel MOSFET's under bias-temperature aging

Abstract: New experimental evidence of positive threshold-voltage shift caused by interface state generation under positive bias-temperature (BT) aging is presented. Interface states were estimated for MOSFET's using low-frequency (8-Hz) C-V measurement, which was carried out by a lock-in technique. Generated acceptor-type interface states are distributed between the midgap and the conduction-band edge in the forbidden gap. Time( t ) and temperature( T ) dependence for threshold-voltage shift ( \deltaV_{T} ) is represented experimentally as \deltaV_{T}\infin log (t/t_{0}) , where t_{0}^{-1} \infin \exp (-1.0 eV/kT) . The positive V T shift appears faster for MOSFET's fabricated with dry O 2 oxides as gate insulator than for those with HCI oxides. It is also shown that the V T shift is always larger than the flat-band voltage shift caused by interface state generation under negative BT aging. Generated interface states are distributed in the entire forbidden gap, differing from the case of positive BT aging.

Transconductance degradation in thin-Oxide MOSFET's

Abstract: In this work we investigate the transconductance degradation effect which occurs in thin-oxide FET's due to finite inversion-layer capacitance and to the decrease of the electron mobility as the electric field increases. Capacitance measurements are performed at room and at liquid-nitrogen temperature on 10 nm oxide FET's, and the data compared with a classical and a quantum-mechanical model extended to take into account a non-uniform doping profile in the silicon substrate. Accurate mobility determinations are performed accounting for the non-uniform distribution of the mobile charge along the channel. Design trade-offs for submicron FET's are finally discussed.

Semiconductor integrated circuit device and manufacture thereof

Abstract: PURPOSE: To obtain an IC which has an MOSFET capable of being coexistent with a microminiaturized high speed bipolar transistor by forming a semiconductor region which reduces the impurity density toward the depthwise direction and again increases the impurity density. CONSTITUTION: B of a p type impurity 5 is introduced in advance on an n + type buried layer to form a p type well 14 on an epitaxial layer, p type diffusion is performed from above and below after epitaxial layer is grown, thereby shortening the time of well diffusion, gush-up diffusion of an n + type buried layer 8 is reduced. Accordingly, even when the thickness of the epitaxial layer is thin, the withstand voltage of the bipolar transistor is not deteriorated, and a high s]eed bipolar transistor can be coexisted with an MOSFET. The epitaxial layer is grown to the thickness of approx. 4μm, a high speed transistor which has the emitter depth of 3μm can be designed by the bipolar element, the isolation area can be reduced by coexisting the well diffusing step and the isolation diffusion step from above and below, thereby improving the integration. COPYRIGHT: (C)1984,JPO&Japio

Switched capacitor gain stage with offset and switch feedthrough cancellation scheme

Abstract: SWITCHED CAPACITOR GAIN STAGE WITH OFFSET AND SWITCH FEEDTHROUGH CANCELLATION SCHEME Gideon Amir Yusuf Haque Roubik Gregorian ABSTRACT An operational amplifier gain stage utilizing switched capacitor resistor equivalent circuits is designed utilizing a delayed clock reference signal (0D, ?D) in a unique manner, thereby eliminating the effects of spurious error voltages (Es) generated when utilizing metal oxide silicon field effect transistors as switches (12, 15, 21, 23, 25). The single remaining MOSFET switch (21) which will contribute a spurious voltage component to the output of the operational amplifier gain stage is designed in such a manner as to minimize the spurious voltage generated during operation of the MOSFET switch.A single dummy switch (31) is utilized to further minimize the spurious voltage generated by this single MOSFETswitch.

DMOS With gate protection diode formed over base region

Abstract: A semiconductor integrated circuit device is provided to include a vertical type MOSFET and a gate protection element for the MOSFET. The vertical type MOSFET is made up of a silicon layer of n-type conductivity formed on an n+ -type silicon substrate, a base region of p-type conductivity formed in the surface of the silicon layer of n-type conductivity, an n+ -type source region provided in the base region, and a gate electrode formed on a portion of the base region through a gate insulating film. The silicon substrate serves as the drain. The gate protection element is formed of a polycrystalline silicon layer which is provided on the base region through an insulating film and includes at least one pn junction. By virtue of forming the gate protection element over the base region rather than directly over the substrate, a more stable operation is achieved.

Switched-capacitor conductance-control of variable transconductance elements

Abstract: Many signal processing applications of practical importance (for example, continuous-signal filtering) require high-precision temperature-insensitive transconductance elements. In accordance with one feature of this invention, a reference transconductance element is included in a control loop. The element consists of a MOSFET device or a MOSFET circuit in the loop. In the loop, the transconductance of the reference element is determined solely by the value and switching period of a switched-capacitor. The transconductance of the element is in effect thereby precisely matched against the conductance of the switched-capacitor. As the temperature of the chip varies, a control voltage is generated in the loop to maintain the transconductance of the reference element constant. This same control voltage is applied to other similar elements included in circuits (for example, filters) on the chip. In that way, the transconductances of these other elements are also matched to that of the switched-capacitor. Significantly, the time constants in the circuits are thus made substantially temperature-insensitive, being proportional only to the product of the switching period of the switched-capacitor and to the ratio of capacitances on the chip. In accordance with another feature of the invention, a switched-capacitor and a reference voltage source are utilized as a standard for establishing a prespecified current and maintaining it substantially independent of temperature variations. In one specific embodiment, this current is in turn utilized to bias an associated differential pair thereby to maintain its transconductance temperature-insensitive.

Enhancement type InP metal‐insulator‐semiconductor field‐effect transistor with plasma anodic aluminium oxide as the gate insulator

Abstract: Enhancement type InP metal‐insulator‐semiconductor field‐effect transistors were fabricated using plasma anodic aluminium oxide as the gate insulator. The effective electron mobilities in the surface channel are 1250 cm2/Vs and 2000 cm2/Vs at 300 and 80 K, respectively. The drift of the drain current at 300 K ceases a few minutes after applying a gate voltage and stable dc operation is observed over several hours.