Showing papers on "Polycrystalline silicon published in 2021"

Design rules for high-efficiency both-sides-contacted silicon solar cells with balanced charge carrier transport and recombination losses

Abstract: The photovoltaic industry is dominated by crystalline silicon solar cells. Although interdigitated back-contact cells have yielded the highest efficiency, both-sides-contacted cells are the preferred choice in industrial production due to their lower complexity. Here we show that omitting the layers at the front side that provide lateral charge carrier transport is the key to excellent optoelectrical properties for both-sides-contacted cells. This results in a conversion efficiency of 26.0%. In contrast to standard industrial cells with a front side p–n junction, this cell exhibits the p–n junction at the back surface in the form of a full-area polycrystalline silicon-based passivating contact. A detailed power-loss analysis reveals that this cell balances electron and hole transport losses as well as transport and recombination losses in general. A systematic simulation study led to some fundamental design rules for future >26% efficiency silicon solar cells and demonstrates the potential and the superiority of these back-junction solar cells. Front- and back-junction silicon photovoltaics dominate the market thanks to a lower manufacturing complexity compared with that of other device designs yet advances in efficiency remain elusive. Richter et al. now present an optimized design for the front and back junctions that leads to a 26.0%-efficient cell.

Mobility–stability trade-off in oxide thin-film transistors

Abstract: Thin-film transistors based on amorphous oxide semiconductors could be used to create low-cost backplane technology for large flat-panel displays. However, a trade-off between mobility and stability has limited the ability of such devices to replace current polycrystalline silicon technologies. Here we show that the sensitivity of amorphous oxide semiconductors to externally introduced impurities and defects is determined by the location of the conduction-band minimum and the relevant doping ability. Using bilayer-structured thin-film transistors, we identify the exact charge-trapping position under bias stress, which shows that the Fermi-level shift in the active layer can occur via electron donation from carbon-monoxide-related impurities. This mechanism is highly dependent on the location of the conduction-band minimum and explains why carbon-monoxide-related impurities greatly affect the stability of high-mobility indium tin zinc oxide transistors but not that of low-mobility indium gallium zinc oxide transistors. Based on these insights, we develop indium tin zinc oxide transistors with mobilities of 70 cm2 (V s)–1 and low threshold voltage shifts of –0.02 V and 0.12 V under negative- and positive-bias temperature stress, respectively. By understanding the origins of instability in high-mobility amorphous oxide transistors, ultrastable thin-film transistors with mobilities of 70 cm2 (V s)–1 can be fabricated.

Optimum Hydrogen Injection in Phosphorus-Doped Polysilicon Passivating Contacts.

Abstract: It has previously been shown that ex situ phosphorus-doped polycrystalline silicon on silicon oxide (poly-Si/SiOx) passivating contacts can suffer a pronounced surface passivation degradation when ...

Solution-Doped Polysilicon Passivating Contacts for Silicon Solar Cells.

Abstract: In this work, we present a simple and efficient solution-doping process for preparing high-quality polycrystalline silicon (poly-Si)-based passivating contacts. Commercial phosphorus or boron-doping solutions are spin-coated on crystalline silicon (c-Si) wafers that feature SiO2/poly-Si layers; the doping process is then activated by thermal annealing at high temperatures in a nitrogen atmosphere. With optimized n- and p-type solution doping and thermal annealing, n- and p-type poly-Si passivating contacts featuring simultaneously a low contact recombination parameter (J0c) of 2.4 and 12 fA/cm2 and a low contact resistivity (ρc) of 29 and 20 mΩ·cm2 are achieved, respectively. Taking advantage of the single-sided nature of these solution-doping processes, c-Si solar cells with poly-Si passivating contacts of opposite polarity on the respective wafer surfaces are fabricated using a simple coannealing process, achieving the best power conversion efficiency (PCE) of 18.5% on a planar substrate. Overall, the solution-doping method is demonstrated to be a simple and promising alternative to gas/ion implantation doping for poly-Si passivating-contact manufacturing.

Multi-Level Memory Comprising Low-Temperature Poly-Silicon and Oxide TFTs

Abstract: In this letter, a new multi-level memory cell using low-temperature polycrystalline silicon and oxide (LTPO) thin-film transistor (TFT) backplane is proposed. The multi-bit data storage can be achieved with a simple structure of two transistors and a capacitor, which controls the threshold voltage of a memory cell transistor exactly. In a memory cell, the low-temperature polycrystalline silicon (LTPS) TFT provides excellent stability against bias stress or current stress. In addition, the oxide semiconductor TFT enables the long-term data storage by virtue of its extremely low off-state leakage current. The proposed memory is fabricated with the LTPO TFT process which includes p-type LTPS and n-type oxide TFTs. Furthermore, the implementation of the multi-level property is successfully verified by measured results.

Charge-carrier dynamics for silicon oxide tunneling junctions mediated by local pinholes

Abstract: Summary Tunnel oxide passivating contact (TOPCon) technology has attracted much attention in the crystalline silicon (c-Si) photovoltaic (PV) community due to overwhelming advantages for device efficiency and cost. However, fundamental device physics of the core structure of TOPCon (i.e., the polycrystalline silicon [poly-Si]/silicon oxide [SiOx]/c-Si junction), are not yet fully understood. Here, we conduct extensive experiments and simulations to clarify the underlying dynamics of the junction featuring local pinholes, including pinhole formation processes and charge-carrier transport mechanisms. The pinhole formation process is investigated by following the film dynamics, which suggest that stress due to thermal expansion is probably responsible for SiOx film fracture. The carrier transport mechanism of the poly-Si/SiOx/Si junction is numerically investigated, revealing that tunneling charge-carrier transport couples with direct transport through pinholes. Moreover, a detailed current-recombination analysis in conjunction with predictions of device efficiencies is demonstrated, providing a specific technical route to promote device efficiencies to 27%.

Individual efficiencies of a polycrystalline silicon PV cell versus temperature

Abstract: The present paper is about an investigation on the temperature dependence of efficiencies of individual energetic process (Absorption efficiency, Thermalization efficiency, Thermodynamic efficiency and Fill factor) and overall conversion efficiencies of a polycrystalline silicon solar cell which has been investigated in temperature range 10–50 °C. All these individual efficiencies present a decrease versus the increase of the temperature. However, the thermodynamic efficiency and the fill factor are more sensitive to the temperature increase more than the absorption and thermalization efficiencies. The thermodynamic efficiency and the fill factor degradation is explained by decrease of open circuit voltage in temperature. The performance parameters as open circuit voltage, maximum power and the overall efficiencies are found to decrease with temperature while the short circuit current is observed an increase. The resistance of the semiconductor decreases with the increase of the temperature. The minoritary carriers charge acquire excessive kinetic energy which can exceed the gap energy causing an over-excitement when the temperature increase. However, this over-excitement of the minoritary carriers charge does not participate to the external current improvement.

Effect of Hot Zone Design on Polycrystalline Silicon Ingot Growth Process by Seeded Directional Solidification

Abstract: This paper uses the finite element method for numerical simulation and builds a transient global model to simulate polycrystalline silicon ingot growing process in CGsim software. The transient global model is verified through experiments. In addition, the influence of the width and height of the bottom of the side insulation on the temperature field, power consumption and melt-crystal interface (m/c interface) of the solidification process are analyzed. And a new hot zone design method is proposed to protect seed crystal silicon. The results show that the residual height of the seed crystal is increased by 4.5 mm through this design. And increasing the width and height of the side insulation bottom can effectively reduce the power consumption by 5 kW and improve the crystal growth interface, which helps to improve the crystal quality and reduce the cost. This study will provide some references for the optimization of polycrystalline silicon ingot growing process.

Obtaining simultaneously high crystallinity and sub-bandgap absorption in femtosecond laser hyperdoped black silicon using ion beam etching

Abstract: Femtosecond laser sulfur hyperdoped silicon (fs-hSi) is capable of absorbing photons in the infrared spectral range while simultaneously exhibiting negligible reflection. However, laser processing creates detrimental amorphous and polycrystalline silicon surface layers impairing electronic properties, especially reducing minority charge carrier lifetimes. This paper demonstrates how to selectively remove these disadvantageous layers by ion beam etching, while crystalline IR-absorbing silicon underneath is left. The increase in silicon crystallinity is quantified by laterally probing the fs-hSi samples with Raman spectroscopy.

Boron Spin-On Doping for Poly-Si/SiOx Passivating Contacts

Abstract: Herein, we fabricate and characterize p-type passivating contacts based on industrial intrinsic polycrystalline silicon (poly-Si)/thermal-SiOx/n-type crystalline Si (c-Si) substrates using a spin-o...

Life Cycle Assessment of Crystalline Silicon Wafers for Photovoltaic Power Generation

Abstract: A life cycle assessment(LCA) was conducted over the modified Siemens method polycrystalline silicon(S-P-Si) wafer, the modified Siemens method single crystal silicon(S-S-Si) wafer, the metallurgical route polycrystalline silicon(M-P-Si) wafer and the metallurgical route single crystal silicon(M-S-Si) wafer from quartzite mining to wafer slicing in China. A large amount of data was investigated from relevant literature and factories in this study. Based on the contribution analysis and sensitivity analysis, the key points for improvement were found. The result included primary energy demand (PED), chemical oxygen demand (COD), SO2, NH3-N, NOX, CO2, and industrial water use (IWU). The above seven indexes were weighted and then added to get China’s thirteenth five-year plan for energy conservation and emission reduction total environmental impact indexes(ECER-135) of S-P-Si wafer, S-S-Si wafer, M-P-Si wafer and M-S-Si wafer were 1.47 × 10−9, 2.12 × 10−9, 3.30 × 10−10 and 1.22 × 10−9 respectively. The ECER-135 of silicon wafers purified with modified Siemens method was higher than that purified with metallurgical route by 3.1 times on average; the ECER-135 of single crystal silicon wafers production was larger than that of polysilicon wafers production by 2.3 times on average. When the four kinds of silicon wafers were used to generate the same amount of electricity for photovoltaic modules, the ECER-135 of S-P-Si wafer, S-S-Si wafer and M-S-Si wafer were 3.3, 4.5 and 2.8 times of that of M-P-Si wafer respectively. During the whole production process, the electricity consumption was of the highest sensitivity for ECER-135. PED had the highest contribution to the ECER-135 for four kinds of silicon wafers, mainly due to the use of thermal power. If hydropower were used instead of thermal power, the ECER-135 could be reduced by 46% to 62%.

Demonstration of tantalum as a structural material for MEMS thermal actuators.

Abstract: This work demonstrates the processing, modeling, and characterization of nanocrystalline refractory metal tantalum (Ta) as a new structural material for microelectromechanical system (MEMS) thermal actuators (TAs). Nanocrystalline Ta films have a coefficient of thermal expansion (CTE) and Young’s modulus comparable to bulk Ta but an approximately ten times greater yield strength. The mechanical properties and grain size remain stable after annealing at temperatures as high as 1000 °C. Ta has a high melting temperature (Tm = 3017 °C) and a low resistivity (ρ = 20 µΩ cm). Compared to TAs made from the dominant MEMS material, polycrystalline silicon (polysilicon, Tm = 1414 °C, ρ = 2000 µΩ cm), Ta TAs theoretically require less than half the power input for the same force and displacement, and their temperature change is half that of polysilicon. Ta TAs operate at a voltage 16 times lower than that of other TAs, making them compatible with complementary metal oxide semiconductors (CMOS). We select α-phase Ta and etch 2.5-μm-thick sputter-deposited films with a 1 μm width while maintaining a vertical sidewall profile to ensure in-plane movement of TA legs. This is 25 times thicker than the thickest reactive-ion-etched α-Ta reported in the technical literature. Residual stress sensitivities to sputter parameters and to hydrogen incorporation are investigated and controlled. Subsequently, a V-shaped TA is fabricated and tested in air. Both conventional actuation by Joule heating and passive self-actuation are as predicted by models.

A Simple Model for the High Temperature Oxidation Kinetics of Silicon Nanoparticle Aggregates

Abstract: Silicon nanoparticles are an emerging and promising material in many fields including electronics, catalysis, and biomaterial engineering. Synthesis in the gas phase via aerosol routes allows tuning and engineering material features such as primary particle size distribution, agglomerate size distribution, crystallite size, and morphology. Proper control of these features as well as post-synthesis processing such as surface oxidation is very relevant for making the nanoparticles chemically stable. Therefore, a kinetic expression for determining the extent of oxidation in silicon nanoparticles is necessary. Significant work has been devoted to understanding the kinetics of monocrystalline silicon, and generally accepted models such as the one by Deal and Grove provide a very accurate description of bulk silicon oxidation. However, these models are not as accurate for the first hundreds of angstroms of the oxidation. While this might be acceptable for bulk wafers, it has critical results for silicon nanoparticles with diameters around such range. Furthermore, many applications involve silicon nanoparticle aggregates with a shape far away from perfect spheres. For this reason, in this work, we propose an expression for the parabolic oxidation kinetics of polycrystalline silicon nanoparticle aggregates at 1000 °C with surface area in the range of 3 to 19 m2/g. and crystallite sizes from 50 to 70 nm. The activation energy of the process is also reported to be linked to the crystallite size.

Polycrystalline-Silicon-MOSFET-Based Capacitorless DRAM With Grain Boundaries and Its Performances

Abstract: In this work, a capacitorless one-transistor dynamic random access memory (1T-DRAM) based on a polycrystalline silicon (poly-Si) metal–oxide–semiconductor field-effect transistor was designed and analyzed through a technology computer-aided design (TCAD) simulation. A poly-Si thin film was utilized within the device because of several advantages, including its low fabrication cost and the feasibility of its use in high-density three-dimensional (3D) memory arrays. An asymmetric dual-gate structure is proposed to perform the write “1” operation and achieve high retention characteristics. The proposed 1T-DRAM cell demonstrates a high sensing margin of $8.73~\mu \text{A} / \mu \text{m}$ and a high retention time of 704.4 ms compared to previously reported 1T-DRAMs, even at a high temperature. In addition, the effect of grain boundaries on the memory performance of the proposed device was investigated, and the results validated the excellent reliability of its retention characteristics even in the presence of grain boundaries (>64 ms at $T =358$ K).

Raman Study of Polycrystalline Si3N4 Irradiated with Swift Heavy Ions

Abstract: A depth-resolved Raman spectroscopy technique was used to study the residual stress profiles in polycrystalline silicon nitride that was irradiated with Xe (167 MeV, 1 × 1011 cm−2 ÷ 4.87 × 1013 cm−2) and Bi (710 MeV, 1 × 1011 cm−2 ÷ 1 × 1013 cm−2) ions. It was shown that both the compressive and tensile stress fields were formed in the irradiated specimen, separated by a buffer zone that was located at a depth that coincided with the thickness of layer, amorphized due to multiple overlapping track regions. The compressive stresses were registered in a subsurface region, while at a greater depth, the tensile stresses were recorded and their levels reached the maximum value at the end of ion range. The size of the amorphous layer was evaluated from the dose dependence of the full width at half maximum (FWHM) (FWHM of the dominant 204 cm−1 line in the Raman spectra and scanning electron microscopy.

Etching with electron beam-generated plasmas: Selectivity versus ion energy in silicon-based films

Abstract: In the ideal case, plasma-enhanced atomic layer etching enables the ability to not only remove one monolayer of material but also leave adjacent layers undamaged. This dual mandate requires fine control over the flux of species to ensure efficacy, while maintaining an often arduously low ion energy. Electron beam-generated plasmas are well-suited for etching at low ion energies as they are generally characterized by highly charged particle densities (1010–1011 cm−3) and low electron temperatures (<1.0 eV), which provide the ability to deliver a large flux of ions whose energies are <5 eV. Raising the ion energy with substrate biasing thus enables process control over an energy range that extends down to values commensurate with the bond strength of most material systems. In this work, we discuss silicon nitride etching using pulsed, electron beam-generated plasmas produced in argon-SF6 backgrounds. We pay particular attention to the etch rates and selectivity versus oxidized silicon nitride and polycrystalline silicon as a function of ion energy from a few eV up to 50 eV. We find the blanket etch rate of Si3N4 to be in the range of 1 A/s, with selectivities (versus SiO2 and poly-Si) greater than 10:1 when ion energies are below 30 eV.

Surface Modification Using Assisting Electrodes in Wire Electrical Discharge Machining for Silicon Wafer Preparation

Abstract: This paper outlines notable advances in the wire electrical discharge machining of polycrystalline silicon workpieces for wafer preparation. Our use of assisting electrodes permits the transfer of aluminum particles to the machined surface of the polycrystalline silicon workpieces, to enhance conductivity and alter surface topography regardless of the silicon’s crystallographic structure and diamond-type lattice. This in-process surface modification technique was shown to promote material removal and simultaneously preserve the integrity of the machined surfaces with preferable surface textures. In the validation experiment, the 25 mm-thick assisting electrodes deposited a notable concentration of aluminium on the machined surface (~3.87 wt %), which greatly accelerated the rate of material removal (~9.42 mg/s) with minimal surface roughness (Sa ~5.49 μm) and moderate skewness (−0.23). The parameter combination used to obtain the optimal surface roughness (Sa 2.54 μm) was as follows: open voltage (80 V), electrical resistance (1.7 Ω), pulse-on time (30 μs), and electrode thickness (15 mm). In multiple objective optimization, the preferred parameter combination (open voltage = 80 V, resistance = 1.4 Ω, pulse-on time = 60 μs, and assisting electrode thickness = 25 mm) achieved the following appreciable results: surface modification of 3.26 ± 0.61 wt %, material removal rate of 7.08 ± 2.2 mg/min, and surface roughness of Sa = 4.3 ± 1.67 μm.

Size Effects of Poly-Si Formed by Laser Annealing With Periodic Intensity Distribution on the TFT Characteristics

Abstract: Currently, low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs), which are characterized by high mobility of electrons, are fabricated by excimer laser annealing. High mobility in low-temperature polycrystalline silicon is achieved by controlling the grain size to approximately 300 nm. However, with future potential growth of active-matrix organic light-emitting diodes in terms of their increasing use as backlight in active matrix micro-LEDs, even higher mobility is required. One of the methods to improve mobility is to produce grains of sizes above 300 nm. However, as far as we know, there are no reports of investigating the dependence between the device characteristics and the grain size of above 300 nm. In this study, we examine the possibility of controlling the grain size above approximately 350 nm by laser annealing with an intensity distribution and investigate the grain size dependence of the TFT characteristics. We show that the grain size can be controlled approximately in the range of 1–2.5 $\mu \text{m}$ , and mobility of 248±28 cm2 V−1s−1 is achieved at a grain size of 2.5 $\mu \text{m}$ . Furthermore, we compare the device characteristics of the step-and-repeat and scan annealing and verify that the device characteristics do not deteriorate even during scan annealing. The study confirms that it is technically possible to produce LTPS with grain sizes controlled in the range of 1–2.5 $\mu \text{m}$ for customizing device characteristics.