Showing papers on "Programmable logic array published in 2014"

Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies

Abstract: Memristors are novel devices, useful as memory at all hierarchies. These devices can also behave as logic circuits. In this paper, the IMPLY logic gate, a memristor-based logic circuit, is described. In this memristive logic family, each memristor is used as an input, output, computational logic element, and latch in different stages of the computing process. The logical state is determined by the resistance of the memristor. This logic family can be integrated within a memristor-based crossbar, commonly used for memory. In this paper, a methodology for designing this logic family is proposed. The design methodology is based on a general design flow, suitable for all deterministic memristive logic families, and includes some additional design constraints to support the IMPLY logic family. An IMPLY 8-bit full adder based on this design methodology is presented as a case study.

FPGA Security: Motivations, Features, and Applications

Abstract: Since their inception, field-programmable gate arrays (FPGAs) have grown in capacity and complexity so that now FPGAs include millions of gates of logic, megabytes of memory, high-speed transceivers, analog interfaces, and whole multicore processors. Applications running in the FPGA include communications infrastructure, digital cinema, sensitive database access, critical industrial control, and high-performance signal processing. As the value of the applications and the data they handle have grown, so has the need to protect those applications and data. Motivated by specific threats, this paper describes FPGA security primitives from multiple FPGA vendors and gives examples of those primitives in use in applications.

FPGA-RPI: A Novel FPGA Architecture With RRAM-Based Programmable Interconnects

Abstract: In this paper we introduce a novel field programmable gate array (FPGA) architecture with resistive random access memory (RRAM)-based programmable interconnects (FPGA-RPI). Programmable interconnects are the dominant part of FPGA. We use RRAMs to build programmable interconnects, and optimize their structures by exploiting opportunities that emerge in RRAM-based circuits. FPGA-RPI can be fabricated by the existing CMOS-compatible RRAM process. Using an advanced placement and routing tool named VPR-RPI which was developed to deal with the novel architecture, a customized CAD flow is provided for FPGA-RPI. Results show that the programmable interconnects of FPGA-RR have a 96% smaller footprint, 55% higher performance, and 79% lower power consumptions compared to other FPGA counterparts.

Hardware obfuscation using PUF-based logic

Abstract: There is a great need to develop universal and robust techniques for intellectual property protection of integrated circuits. In this paper, we introduce techniques for the obfuscation of an arbitrary circuit by using physical unclonable functions (PUFs) and programmable logic. Specifically, we introduce the notion of PUF-based logic which can be configured to be functionally equivalent to any arbitrary design, as well as a new architecture for wire merging that obfuscates signal paths exponentially. We systematically apply our techniques in such a way so as to maximize obfuscation while minimizing area and delay overhead. We analyze our techniques on popular benchmark circuits and show them to be resilient against very powerful reverse engineering attacks in which the adversary has knowledge of the complete netlist along with the ability to read and write to any flip-flop in the circuit.

Trends of CPU, GPU and FPGA for high-performance computing

Abstract: Floating-point computing with more than one TFLOP of peak performance is already a reality in recent Field-Programmable Gate Arrays (FPGA). General-Purpose Graphics Processing Units (GPGPU) and recent many-core CPUs have also taken advantage of the recent technological innovations in integrated circuit (IC) design and had also dramatically improved their peak performances. In this paper, we compare the trends of these computing architectures for high-performance computing and survey these platforms in the execution of algorithms belonging to different scientific application domains. Trends in peak performance, power consumption and sustained performances, for particular applications, show that FPGAs are increasing the gap to GPUs and many-core CPUs moving them away from high-performance computing with intensive floating-point calculations. FPGAs become competitive for custom floating-point or fixed-point representations, for smaller input sizes of certain algorithms, for combinational logic problems and parallel map-reduce problems.

Field programmable gate array utilizing two-terminal non-volatile memory

Abstract: Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.

Design and Synthesis of Ultralow Energy Spin-Memristor Threshold Logic

Abstract: A threshold logic gate performs weighted sum of multiple inputs and compares the sum with a threshold We propose spin-memeristor threshold logic (SMTL) gates, which employ a memristive cross-bar array to perform current-mode summation of binary inputs, whereas the low-voltage fast-switching spintronic threshold devices carry out the threshold operation in an energy efficient manner Field-programmable SMTL gate arrays can operate at a small terminal voltage of ∼50 mV, resulting in ultralow power consumption in gates as well as programmable interconnect networks We evaluate the performance of SMTL using threshold logic synthesis Results for common benchmarks show that SMTL-based programmable logic hardware can be more than 100 × energy efficient than the state-of-the-art CMOS field-programmable gate array

Impact of technology scaling on the combinational logic soft error rate

Abstract: Experimental results from alpha particle irradiation of 40-nm, 28-nm and 20-nm bulk technology circuits operating in the GHz range suggest that the combinational logic soft error rate (SER) per logic gate decreases with scaling. This rate of decrease for the logic SER with scaling, however, is not as high as that of the latch SER. As a result, the proportion of combinational logic soft errors at the chip level is shown to increase. Results suggest that alpha-particle logic SER of average sized circuits is about 20% of the latch SER at 20-nm node while it is only 10% at 40-nm at 500 MHz. Moreover, the frequency at which combinational logic SER exceeds latch SER decreases with scaling. Factors that influence logic soft error scaling trends, such as sensitive area, transient pulse-widths and latch characteristics, are estimated through simulations and soft-error rate predictions for future technology nodes are made.

Logic synthesis and a generalized notation for memristor-realized material implication gates

Abstract: The paper presents new logic synthesis methods for single-output incomplete multi-level binary circuits using Memristor-based material implication gates. The first method follows Lehtonen's assumption of using only two working memristors. The algorithm minimizes the number of implication (IMPLY) gates, which corresponds to minimizing the number of pulses or the delay time. This greedy search method uses essential and secondary essential primes, does not require solving the covering problem, is fast, and produces high quality results. We compare it to other synthesis methods, such as the modified SOP and Exclusive-Or Sum of Products (ESOP) with minimum number of working memristors. We analyze the problem of reduction in IMPLY gate count by adding more working memristors and introduce Imply Sequence Diagrams, a new notation, similar to one used in reversible logic.

Programmable logic device and semiconductor device

Abstract: A programmable logic device includes a plurality of programmable logic elements (PLE) whose electrical connection is controlled by first configuration data. Each of The PLEs includes an LUT in which a relationship between a logic level of an input signal and a logic level of an output signal is determined by second configuration data, an FF to which the output signal of the LUT is input, and an MUX. The MUX includes at least two switches each including first and second transistor. A signal including third configuration data is input to a gate of the second transistor through the first transistor. The output signal of the LUT or an output signal of the FF is input to one of a source and a drain of the second transistor.

Dynamic Adaptive Neural Network Array

Abstract: We present the design-scheme and physical implementation for a Dynamic Adaptive Neural Network Array (DANNA) based upon the work by Schuman and Birdwell [1,2] and using a programmable array of elements constructed with a Field Programmable Gate Array (FPGA). The aim of this paper is to demonstrate how a single programmable neuromorphic element can be designed to support the primary components of a dynamic and adaptive neural network, e.g. a neuron and a synapse, and be replicated across a FPGA to yield a reasonably large programmable DANNA of up to 10,000 neurons and synapses. We describe element programmability, how the dynamic components of a neuron and synapse are supported, and the structure used to support the monitoring and control interface. Finally, we present initial results from simulations of the hardware, the projected performance of the array elements and the physical implementation of a DANNA on a Xilinx FPGA.

Programmable Resistive-Switch Nanowire Transistor Logic Circuits

Abstract: Programmable logic arrays (PLA) constitute a promising architecture for developing increasingly complex and functional circuits through nanocomputers from nanoscale building blocks. Here we report a novel one-dimensional PLA element that incorporates resistive switch gate structures on a semiconductor nanowire and show that multiple elements can be integrated to realize functional PLAs. In our PLA element, the gate coupling to the nanowire transistor can be modulated by the memory state of the resistive switch to yield programmable active (transistor) or inactive (resistor) states within a well-defined logic window. Multiple PLA nanowire elements were integrated and programmed to yield a working 2-to-4 demultiplexer with long-term retention. The well-defined, controllable logic window and long-term retention of our new one-dimensional PLA element provide a promising route for building increasingly complex circuits with nanoscale building blocks.

General structure for computational random access memory (CRAM)

Abstract: A cell array includes a logic connection line, a plurality of bit selection lines, and a plurality of cells. Each cell includes a memory element connected to a respective bit selection line and a logic switching element that selectively connects the memory element to the logic connection line. When logic switching elements of multiple separate cells connect their respective memory elements to the logic connection line, the memory elements connected to the logic connection line operate as a logic device with an output of the logic device stored in one of the memory elements.

Low-power programmable-logic cell arrays using nonvolatile complementary atom switch

Abstract: Programmable-logic cell that utilizes complementary atom switch (CAS) is fabricated using 65-nm node CMOS process. A 16-bit ALU is implemented and demonstrated on a 24×24 programmable-logic cell array including 645kbit CAS for both routing switches and configuration memories. Comparing the conventional cell design using CMOS routing multiplexer (MUX), the proposed programmable-logic cell array performs 60% active power saving and 3 times faster operation.

Memristive Stateful Logic

Abstract: Memristive stateful logic refers to a form of computational logic in which memristors both store logic values and perform logical operations on these values. We present a generalized form of memristive stateful logic and define the logic operations realizable in this form. We also consider the CMOS circuitry required for reliable implementation of memristive stateful logic. Furthermore, synthesis of arbitrary Boolean functions and the parallelization of stateful logic to memristive crossbars is presented.

Using soft-sensors in a programmable logic controller

Abstract: A method of operating an intelligent programmable logic controller over a plurality of scan cycles includes the intelligent programmable logic controller selecting one or more soft-sensors available in a control program corresponding to a production unit, each soft-sensor comprising a local parameter or variable used by the control program. The intelligent programmable logic controller determines updated soft-sensor values corresponding to the one or more soft-sensors during each scan cycle and stores those values during each scan cycle on a non-volatile computer-readable storage medium operably coupled to the intelligent programmable logic controller. Additionally, the intelligent programmable logic controller annotates the updated soft-sensor values with automation system context information to generate contextualized data.

Rapid Post-Map Insertion of Embedded Logic Analyzers for Xilinx FPGAs

Abstract: A rapid post-map insertion of an embedded logic analyzer is discussed. The proposed technique makes use of otherwise unused resources in an already-mapped circuit and does not disturb the original placement and routing of the circuit. Using this technique, designers can add debugging circuitry to existing circuits and quickly modify the set of observed signals in just a few minutes instead of waiting for a recompile of their circuit. All tests were performed on a Xilinx Virtex-5 FPGA.

Histogram of oriented gradients front end processing: An FPGA based processor approach

Abstract: The Field Programmable Gate Array (FPGA) implementation of the commonly used Histogram of Oriented Gradients (HOG) algorithm is explored. The HOG algorithm is employed to extract features for object detection. A key focus has been to explore the use of a new FPGA-based processor which has been targeted at image processing. The paper gives details of the mapping and scheduling factors that influence the performance and the stages that were undertaken to allow the algorithm to be deployed on FPGA hardware, whilst taking into account the specific IPPro architecture features. We show that multi-core IPPro performance can exceed that of against state-of-the-art FPGA designs by up to 3.2 times with reduced design and implementation effort and increased flexibility all on a low cost, Zynq programmable system.

A novel quantum-dot cellular automata CLB of FPGA

Abstract: Quantum-dot cellular automata (QCA) is a promising, emerging nano-technology based on single electron effects in quantum dots and molecules. This paper presents design, implementation and simulation of a configurable logic block for a field programmable gate arrays (FPGA) by QCA. Previous works focus on QCA-based FPGA that have fixed logic and programmable interconnection or programmable logic and fixed interconnection; however, proposed structures in this paper have programmable logic and programmable interconnection. The presented look-up table implemented with novel structure which has been allowed as frequently as the read/write operation occurs, also acts as a pipeline. In this paper, we presented novel decoders and multiplexers and implemented with QCA, designed with the minimum number of majority gates and cells. Finally, a new configurable logic block (CLB) is designed, implemented and simulated in the QCA, which used signal distribution network method to avoid the coplanar problem of crossing wires. Also, QCADesigner software is used for detailed layout and QCADesigner attend with HDLQ verilog are used for circuit simulation. The proposed CLB is simulated with programming by the QCADesigner software. The area and delay of QCA-based CLB presented in this paper compared to the CLB based on CMOS, nanomaterial and CNT (32 nm). Results show that proposed CLB will do the task with a minimum clock and can be configured as a FPGA.

Emission Analysis of Hardware Implementations

Abstract: Today, hardware implementations are the basis for many security applications, such as cryptographic ciphers. Such applications are realized using complex combinatorial logic circuits of substantial size. Therefore, understanding the gate-level implementation can be crucial for the attacker. However, Hardware Description Language (HDL) behavioral models and gate-level net list are seldom available for a particular design. Executing software directly on the device to assist in understanding the implementation is one potential solution. However, this may either be infeasible or completely impossible in practice as target devices may be incapable of executing code. Currently, few works have proposed forms of dynamic gate-level analysis of the actual hardware implementations. Moreover, current reverse-engineering techniques based on physical delayering and optical imaging cannot be applied to programmable logic. In this work we present the first dynamic emission analysis of a hardware implementation. This technique does not require any prior knowledge about the target device. Furthermore, it does not require code to be executed by the target. Hardware implementations consist of basic primitives that form the building blocks of complex hardware functions. By individually analyzing each primitive and correlating the corresponding optical images, the emission fingerprint of each primitive can be identified. As a result the hardware implementation of the device can be reconstructed. We present practical results for a common Complex Programmable Logic Device (CPLD). However, the same approach can be applied to hardware implementations in general.

A configurable, programmable and software-defined network on chip

Abstract: The rapidly developing multi-cores integration on a chip requires efficient networking. To catch up the evolvement of on-chip network technologies and reduce the cost of redesign and redeployment, the software-defined solution is required on chip instead of proprietary design and straightforward replacement of hardware. In this paper, we propose the software defined on-chip network (SDNoC), which is a configurable and programmable network on chip with the idea of software defined networking. SDNoC separates on-chip network into the control plane and data forwarding plane, so that control logic is decoupled from the underlying chip hardware, and applications are able to configure the network according to their requirements. The simulation evaluates the SDNoC compared with the static and dynamic routing schemes in the traditional on-chip network, and shows SDNoC is able to improve the network performance and reduce power consumption with the programmable control logic and application-specific configuration.

New Techniques for SET Sensitivity and Propagation Measurement in Flash-Based FPGAs

Abstract: Single-event transients (SETs) remain a concern in field-programmable gate arrays (FPGAs) used for space applications. However, accurate measurement of SETs in FPGAs is challenging. This paper describes a calibrated circuit for on-chip measurement of SETs with a temporal precision better than one gate delay. In addition, a technique to measure the final effect of SETs in clocked, complex circuits is presented. Heavy-ion test results for a ProASIC3L FPGA are reported, highlighting a strong dependence between the VersaTile configuration and input signal state with the SET sensitivity and pulse propagation.

Expanded all-optical programmable logic array based on multi-input/output canonical logic units

Abstract: We present an expanded all-optical programmable logic array (O-PLA) using multi-input and multi-output canonical logic units (CLUs) generation. Based on four-wave mixing (FWM) in highly nonlinear fiber (HNLF), two-input and three-input CLUs are simultaneously achieved in five different channels with an operation speed of 40 Gb/s. Clear temporal waveforms and wide open eye diagrams are successfully observed. The effectiveness of the scheme is validated by extinction ratio and optical signal-to-noise ratio measurements. The computing capacity, defined as the total amount of logic functions achieved by the O-PLA, is discussed in detail. For a three-input O-PLA, the computing capacity of the expanded CLUs-PLA is more than two times as large as that of the standard CLUs-PLA, and this multiple will increase to more than three and a half as the idlers are individually independent.

3D FPGA using high-density interconnect monolithic integration

Abstract: New 3D technology, called "Monolithic Integration", offers very dense 3D interconnect capabilities. In this paper, we propose a 3D FPGA architecture with logic-on-memory approach based on this technology. The routing and computation blocks are splitted into two layers where the logic is placed on the top and memory on the bottom. Using extracted values from layout in 14nm FDSOI technology, typical benchmark circuits are evaluated in the VPR5 toolflow. The results show an area reduction of 55% compared to the 2D FPGA. More importantly, due to the lowered routing congestion, the EDP of the 3D FPGA is improved by 47%.

A Fine-Grain Dynamically Reconfigurable Architecture Aimed at Reducing the FPGA-ASIC Gaps

Abstract: Prior work has shown that due to the overhead incurred in enabling reconfigurability, field-programmable gate arrays (FPGAs) require 21× more silicon area, 3× larger delay, and 10× more dynamic power consumption compared with application-specific integrated circuits (ASICs). We have earlier presented a hybrid CMOS/nanotechnology reconfigurable architecture (NATURE). It uses the concept of temporal logic folding and fine-grain (i.e., cycle-level) dynamic reconfiguration to increase logic density by an order of magnitude. Since logic folding reduces area usage significantly, on-chip communications tend to become localized. To take full advantage of this fact, we propose a new architecture, called fine-grain dynamically reconfigurable (FDR), that consists of an array of homogeneous reconfigurable logic elements (LEs). Each LE can be arbitrarily configured into a lookup table (LUT) or interconnect or a combination of both. This significantly enhances the flexibility of allocating hardware resources between LUTs and interconnects based on application needs. The proposed FDR architecture eliminates most of the long-distance and global wires, which occupy most of the area in conventional FPGAs. Fine-grain dynamic reconfiguration is enabled by local embedded static RAM blocks. The experiments show that, on an average, area, delay, and power are improved by 9.14×, 1.11×, and 1.45×, compared with a conventional FPGA architecture that does not use the concept of logic folding. Compared with NATURE with deep logic folding, area, delay, and power are improved by 2.12×, 3.28×, and 1.74×, respectively. Although this does not eliminate the FPGA-ASIC area/delay/power gaps, it makes progress toward bridging these gaps.

Total Ionizing Dose Characterization of 65 nm Flash-Based FPGA

Abstract: New 65 nm flash-based field programmable gate array with system-on-chip capability is introduced. We present recent Total Ionizing Dose tests results on Smart Fusion 2 Flash-based FPGAs. TID effects at the device and product level are presented and discussed.

Coarse grain clock gating of streaming applications in programmable logic implementations

Abstract: Streaming applications describe a broad class of computing algorithms in areas such as signal processing, media coding and compression, cryptography, video analytics, network touting and packet processing and many others. For many of these applications, programmable logic devices such as FP-GAs are the implementation platform of choice due to their higher flexibility compared to ASICs and lower power consumption and higher performance compared to processors. This paper presents a set of techniques for taking advantage of the streaming character of the algorithm by selectively switching off parts of the circuit that cannot execute, thus saving power. The implementation is integrated into an existing high-level synthesis flow, and applied to a variety of appli-cations, resulting in up to 20% power reduction with a very small additional logic footprint and no loss in throughput. © 2014 European Electronic Chips & Systems design ECSI.

FPGA-based optical network function programmable node

Abstract: The paper presents architecture, implementation and evaluation of optical network function programmable node with hitless inter-function and intra-function switch-over. It supports multiple network functions on opto-electronic programmable hardware providing function-based virtualization and high network performance.