Showing papers on "Sequential logic published in 2010"

Smart molecules at work—mimicking advanced logic operations

Abstract: Molecular logic is an interdisciplinary research field, which has captured worldwide interest. This tutorial review gives a brief introduction into molecular logic and Boolean algebra. This serves as the basis for a discussion of the state-of-the-art and future challenges in the field. Representative examples from the most recent literature including adders/subtractors, multiplexers/demultiplexers, encoders/decoders, and sequential logic devices (keypad locks) are highlighted. Other horizons, such as the utility of molecular logic in bio-related applications, are discussed as well.

Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs

Abstract: Reversible logic has shown potential to have extensive applications in emerging technologies such as quantum computing, optical computing, quantum dot cellular automata as well as ultra low power VLSI circuits. Recently, several researchers have focused their efforts on the design and synthesis of efficient reversible logic circuits. In these works, the primary design focus has been on optimizing the number of reversible gates and the garbage outputs. The number of reversible gates is not a good metric of optimization as each reversible gate is of different type and computational complexity, and thus will have a different quantum cost and delay. The computational complexity of a reversible gate can be represented by its quantum cost. Further, delay constitutes an important metric, which has not been addressed in prior works on reversible sequential circuits as a design metric to be optimized. In this work, we present novel designs of reversible sequential circuits that are optimized in terms of quantum cost, delay and the garbage outputs. The optimized designs of several reversible sequential circuits are presented including the D Latch, the JK latch, the T latch and the SR latch, and their corresponding reversible master-slave flip-flop designs. The proposed master-slave flip-flop designs have the special property that they don't require the inversion of the clock for use in the slave latch. Further, we introduce a novel strategy of cascading a Fredkin gate at the outputs of a reversible latch to realize the designs of the Fredkin gate based asynchronous set/reset D latch and the master-slave D flip-flop. Finally, as an example of complex reversible sequential circuits, the reversible logic design of the universal shift register is introduced. The proposed reversible sequential designs were verified through simulations using Verilog HDL and simulation results are presented.

A noise-assisted reprogrammable nanomechanical logic gate.

Abstract: We present a nanomechanical device, operating as a reprogrammable logic gate, and performing fundamental logic functions such as AND/OR and NAND/NOR. The logic function can be programmed (e.g., from AND to OR) dynamically, by adjusting the resonator's operating parameters. The device can access one of two stable steady states, according to a specific logic function; this operation is mediated by the noise floor which can be directly adjusted, or dynamically "tuned" via an adjustment of the underlying nonlinearity of the resonator, i.e., it is not necessary to have direct control over the noise floor. The demonstration of this reprogrammable nanomechanical logic gate affords a path to the practical realization of a new generation of mechanical computers.

LEAP: Layout Design through Error-Aware Transistor Positioning for soft-error resilient sequential cell design

Abstract: This paper presents a new layout design principle called LEAP which is an acronym for Layout Design through Error-Aware Transistor Positioning. This principle extends beyond traditional layout techniques, such as node separation, and significantly improves the soft error resilience of digital circuits with negligible performance cost. In this study, we applied the LEAP technique to the Dual Interlocked Storage Cell (DICE) and designed a new sequential element called LEAP-DICE. This element retains the circuit topology and transistor sizing of DICE but has a new layout based on the LEAP principle. Radiation experiments using an 180nm CMOS test chip demonstrate that our LEAP-DICE flip-flop encounters 5X fewer errors on average compared to our reference DICE flip-flop, and 2,000X fewer errors on average compared to a conventional D-flip-flop. Our LEAP-DICE flip-flop imposes negligible power and delay costs and 40% flip-flop-level area costs compared to our reference DICE flip-flop.

A new combinational logic minimization technique with applications to cryptology

Abstract: A new technique for combinational logic optimization is described. The technique is a two-step process. In the first step, the non-linearity of a circuit – as measured by the number of non-linear gates it contains – is reduced. The second step reduces the number of gates in the linear components of the already reduced circuit. The technique can be applied to arbitrary combinational logic problems, and often yields improvements even after optimization by standard methods has been performed. In this paper we show the results of our technique when applied to the S-box of the Advanced Encryption Standard (AES [6]). This is an experimental proof of concept, as opposed to a full-fledged circuit optimization effort. Nevertheless the result is, as far as we know, the circuit with the smallest gate count yet constructed for this function. We have also used the technique to improve the performance (in software) of several candidates to the Cryptographic Hash Algorithm Competition. Finally, we have experimentally verified that the second step of our technique yields significant improvements over conventional methods when applied to randomly chosen linear transformations.

Reversible Logic-Based Concurrently Testable Latches for Molecular QCA

Abstract: Nanotechnologies, including molecular quantum dot cellular automata (QCA), are susceptible to high error rates. In this paper, we present the design of concurrently testable latches (D latch, T latch, JK latch, and SR latch), which are based on reversible conservative logic for molecular QCA. Conservative reversible circuits are a specific type of reversible circuits, in which there would be an equal number of 1's in the outputs as there would be on the inputs, in addition to one-to-one mapping. Thus, conservative logic is parity-preserving, i.e., the parity of the input vectors is equal to that of the output vectors. We analyzed the fault patterns in the conservative reversible Fredkin gate due to a single missing/additional cell defect in molecular QCA. We found that if there is a fault in the molecular QCA implementation of Fredkin gate, there is a parity mismatch between the inputs and the outputs, otherwise the inputs parity is the same as outputs parity. Any permanent or transient fault in molecular QCA can be concurrently detected if implemented with the conservative Fredkin gate. The design of QCA layouts and the verification of the latch designs using the QCADesigner and the HDLQ tool are presented.

Synthesizing a novel genetic sequential logic circuit: a push-on push-off switch

Abstract: Design and synthesis of basic functional circuits are the fundamental tasks of synthetic biologists. Before it is possible to engineer higher-order genetic networks that can perform complex functions, a toolkit of basic devices must be developed. Among those devices, sequential logic circuits are expected to be the foundation of the genetic information-processing systems. In this study, we report the design and construction of a genetic sequential logic circuit in Escherichia coli. It can generate different outputs in response to the same input signal on the basis of its internal state, and 'memorize' the output. The circuit is composed of two parts: (1) a bistable switch memory module and (2) a double-repressed promoter NOR gate module. The two modules were individually rationally designed, and they were coupled together by fine-tuning the interconnecting parts through directed evolution. After fine-tuning, the circuit could be repeatedly, alternatively triggered by the same input signal; it functions as a push-on push-off switch.

Multiple Transient Faults in Combinational and Sequential Circuits: A Systematic Approach

Abstract: Transient faults in logic circuits are becoming an important reliability concern for future technology nodes. Radiation-induced faults have received significant attention in recent years, while multiple transients originating from a single radiation hit are predicted to occur more often. Furthermore, some effects, like reconvergent fanout-induced glitches, are more pronounced in the case of multiple faults. Therefore, to guide the design process and the choice of circuit optimization techniques, it is important to model multiple faults and their propagation through logic circuits, while evaluating the changes in error rates resulting from multiple simultaneous faults. In this paper, we show how output error probabilities change with increasing number of simultaneous faults and we also analyze the impact of multiple errors in state flip-flops, during the cycles following the cycle when fault(s) occurred. The results obtained using the proposed framework show that output error probability resulting from multiple-event transient or multiple-bit upsets can vary across different outputs and different circuits by several orders of magnitude. The results also show that the impact of different masking factors also varies across circuits and this information can be valuable for customizing protection techniques.

Constructing Online Testable Circuits Using Reversible Logic

Abstract: With the advent of nanometer technology, circuits are more prone to transient faults that can occur during its operation. Of the different types of transient faults reported in the literature, the single-event upset (SEU) is prominent. Traditional techniques such as triple-modular redundancy (TMR) consume large area and power. Reversible logic has been gaining interest in the recent past due to its less heat dissipation characteristics. This paper proposes the following: 1) a novel universal reversible logic gate (URG) and a set of basic sequential elements that could be used for building reversible sequential circuits, with 25% less garbage than the best reported in the literature; (2) a reversible gate that can mimic the functionality of a lookup table (LUT) that can be used to construct a reversible field-programmable gate array (FPGA); and (3) automatic conversion of any given reversible circuit into an online testable circuit that can detect online any single-bit errors, including soft errors in the logic blocks, using theoretically proved minimum garbage, which is significantly lesser than the best reported in the literature.

Non-Volatile Magnonic Logic Circuits Engineering

Abstract: We propose a concept of magnetic logic circuits engineering, which takes an advantage of magnetization as a computational state variable and exploits spin waves for information transmission. The circuits consist of magneto-electric cells connected via spin wave buses. We present the result of numerical modeling showing the magneto-electric cell switching as a function of the amplitude as well as the phase of the spin wave. The phase-dependent switching makes it possible to engineer logic gates by exploiting spin wave buses as passive logic elements providing a certain phase-shift to the propagating spin waves. We present a library of logic gates consisting of magneto-electric cells and spin wave buses providing 0 or p phase shifts. The utilization of phases in addition to amplitudes is a powerful tool which let us construct logic circuits with a fewer number of elements than required for CMOS technology. As an example, we present the design of the magnonic Full Adder Circuit comprising only 5 magneto-electric cells. The proposed concept may provide a route to more functional wave-based logic circuitry with capabilities far beyond the limits of the traditional transistor-based approach.

Sequential Logic Operations with Surface‐Confined Polypyridyl Complexes Displaying Molecular Random Access Memory Features

Abstract: The processing of molecular information is essential for organisms to respond to external/internal stimuli. For example, in vision, a single molecule of 11-cis-retinal is photoisomerized to all-trans-retinal, which starts a cascade of signal transduction pathways that eventually enables us to see. The fact that molecules can be implemented for processing information akin to electronic systems was recognized and demonstrated by the construction of a photo-ionic AND gate by de Silva et al. This opened up an exciting research area that led to a variety of molecular logic systems such as logic gates, half-adders and subtractors, multiplexers, and encoders. Bio-inspired systems have also attracted much attention. The output of these combinatorial systems is exclusively a Boolean function of the current inputs. In contrast, the output of sequential systems is determined by the current state of the system, which is usually a function of the previous input and the present input. This situation thus requires that the molecular-based system must remember information about the previous input, and hence, functions as a basic memory element. Consequently, sequential logic systems are commonly used in the construction of memory devices, delay and storage elements, and finite-state machines. The demonstration of sequential logic operations with molecularbased systems is relatively rare, and includes circuits, molecular keypad locks, 13] and finite-state machines. Furthermore, previous studies on molecular-based logic are almost exclusively based on solution-based chemistry. Recently, we reported the proof-of-principle that 1-based monolayers (Scheme 1) can perform combinatorial logic operations. The system mimics the input and output characteristics of electronic circuitry when using chemical reagents as inputs and the formal oxidation state of the system as the output. Here, we demonstrate a fundamentally new concept towards reversible and reconfigurable sequential logic operations by addressing the memory function of the 1-based monolayers. Interestingly, not only were we able to generate sequential logic circuits with one, two, and even three chemical inputs, but we were also able to use this sequential logic approach to model the memory function of random access memory (RAM). Moreover, by keeping the starting state static or dynamic, delicate control is obtained regarding which kind of logic is performed—combinatorial or sequential logic. A dynamic starting state generates sequential circuits, whereas a static starting state produces combinatorial circuits. For sequential operations with the 1-based monolayer, the presence or absence of an arbitrary chemical input is defined as a logical 1 or 0, respectively. The output or state is dependent on the formal oxidation state of the system, which is monitored by UV/Vis spectroscopy in the transmission mode. The logical outputs 1 and 0 are defined as Os and Os, respectively (See the Supporting Information). For example, a one-input sequential system was designed with Cr ions in an aqueous solution at pH< 1 as the input. The four possible combinations were demonstrated with the same monolayer (Table 1). Only when Cr ions are present and the monolayer is in state 1 (Os) can the logic gate change to state 0 (Os; Table 1, see also Figure S1 in the Supporting Information). Since the current state is variable, the output Scheme 1. The osmium polypyridyl complex used in this study.

Logic circuit and semiconductor device

Abstract: To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10−13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.

Advanced Molecular Logic with Memory Function

Abstract: The steadily growing demand for ever more powerful devices for information processing is expressed in Moore s law, which predicts the duplication of transistor density in an electronic circuit every 18–24 months. Current lithographic processes for microchip production have spatial resolution limits and thus, the quest for alternatives has created elevated interest in the so-called bottom-up approach, that is, the construction of functional (computing) devices from molecular building blocks. Because logic devices are a central component of information technology, the development of molecular systems for logic operations has received special attention. In 1993, de Silva and co-workers provided proof-of-principle that the universality of logic allows its implementation with bistable molecular systems and non-electrical input/output signals. Since then, molecular logic has been extended in many directions, including functional integration, logic reconfiguration, reversible logic, resetting, all-photonic device operation, and signal communication. What started with basic logic gates like AND, OR, INH, and XOR has now reached high complexity, providing molecular mimics for adders– subtractors, encoders–decoders, and multiplexers–demultiplexers. These logic operations have in common that they are combinational in nature, meaning that the history of input application has no consequences for the device function. On the other hand, sequential logic is a function of past inputs, the thus-created current state of the system, and the actual inputs. Hence, sequential logic implies the existence of a memory function. This feature requires the introduction of feedback loops, which connect the output of a logic gate back to one of its inputs (Figure 1). In conventional electronics, sequential logic is applied in the design of memory elements such as flip-flops, latches, and registers. One of the first examples of still rarely reported molecular sequential logic is an OR gate with a feedback described by Raymo et al. They used a “cocktail” of two molecular switches, namely a photochromic spiropyran–merocyanine system and a 4,4’pyridylpyridinium derivative, which is electroactive in its protonated state. Proton transfer enabled switch-to-switch communication and the memorized bit was stable for roughly 11 hours. Recently, the van der Boom group has made progress in the demonstration of advanced molecular sequential logic, including the fundamental functionality of a molecular random-access memory (RAM) and reconfiguration between combinational and sequential logic. The findings of their work will be discussed later in this Highlight. A keypad lock, like that used for user identification at ATM terminals, can be implemented with sequential logic. In 2007, the Shanzer group presented the first molecular keypad lock, based on a pyrene–fluorescein dyad with a siderophoretype linker as a Fe receptor. The fluorescence response of the system relies on the balance between interchromophore energy transfer, pH-dependent fluorescein emission, and Fe-induced fluorescence quenching. By clever exploitation of a pH-dependent kinetic effect on Fe extraction by EDTA (ethylenediamine tetraacetate) as a competitive ligand, input sequences (EDTA and sodium acetate as inputs) can be differentiated through the corresponding fluorescein emission output. If the light excitation of the pyrene energy donor is defined as third input, a three-digit identification number is obtained. On the downside, the kinetic effect imposes certain temporal limitations for the unambiguous differentiation between input sequences. An all-photonic version of a molecular keypad lock with reset function was presented by the groups of Gust and Andr asson. The exclusive application of optical inputs and outputs enables remote operation and clean resetting without accumulation of chemical side products. To implement this feature a triad composed of fulgimide (FG) and dithienylethene (DTE) photochromes linked to a central fluorescent tetraarylporphyrin (P) was designed. Different wavelengths can be used as optical inputs to address the isomerization of Figure 1. General representation of a sequential logic circuit.

Digital Operations with Molecules ― Advances, Challenges, and Perspectives

Abstract: This Review gives a short introduction into molecular logic and focusses then on the latest advances in the field. With regard to complex logic circuits and functions, molecular devices for arithmetic processing (adders and subtractors), multiplexers/demultiplexers, and encoders/decoders are discussed. Further on, the concept of memory for data storage and sequential logic is considered together with the latest results on molecular keypad locks. Molecular logic has been often connected to the future aim of molecular computing. However, albeit the herein described approaches constitute a starting point, major challenges like concatenation of gates, solid state devices and compartmentalization, and alternative concepts (reversible logic, multivalued logic) are waiting ahead. These points are included, as well as a view on alternative applications of molecular logic in bio-inspired approaches, combinatorial chemistry, and materials science.

Optimization of reversible sequential circuits

Abstract: In recent years reversible logic has been considered as an important issue for designing low power digital circuits. It has voluminous applications in the present rising nanotechnology such as DNA computing, Quantum Computing, low power VLSI and quantum dot automata. In this paper we have proposed optimized design of reversible sequential circuits in terms of number of gates, delay and hardware complexity. We have designed the latches with a new reversible gate and reduced the required number of gates, garbage outputs, and delay and hardware complexity. As the number of gates and garbage outputs increase the complexity of reversible circuits, this design will significantly enhance the performance. We have proposed reversible D-latch and JK latch which are better than the existing designs available in literature.

Logical stochastic resonance

Abstract: In a recent publication it was shown that, when one drives a two-state system with two square waves as input, the response of the system mirrors a logical output (NOR/OR). The probability of obtaining the correct logic response is controlled by the interplay between the noise-floor and the nonlinearity. As one increases the noise intensity, the probability of the output reflecting a NOR/OR operation increases to unity and then decreases. Varying the nonlinearity (or the thresholds) of the system allows one to morph the output into another logic operation (NAND/AND) whose probability displays analogous behavior. Thus, the outcome of the interplay of nonlinearity and noise is a flexible logic gate with enhanced performance. Here we review this concept of "Logical Stochastic Resonance" (LSR) and provide details of an electronic circuit system demonstrating LSR. Our proof-of-principle experiment involves a particularly simple realization of a two-state system realized by two adjustable thresholds. We also review CMOS implementations of a simple LSR circuit, and the concatenation of these LSR modules to emulate combinational logic, such as data flip-flop and full adder operations.

Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs

Abstract: Reversible logic has extensive applications in emerging nanotechnologies, such as quantum computing, optical computing, ultra low power VLSI and quantum dot cellular automata. In the existing literature, designs of reversible sequential circuits are presented that are optimized for the number of reversible gates and the garbage outputs. The optimization of the number of reversible gates is not sufficient since each reversible gate is of different computational complexity, and thus will have a different quantum cost and delay. While the computational complexity of a reversible gate can be measured by its quantum cost, the delay of a reversible gate is another parameter that can be optimized during the design of a reversible sequential circuit. In this work, we present novel designs of reversible latches that are optimized in terms of quantum cost, delay and the garbage outputs. The optimized designs of reversible latches presented in this work are the D Latch, JK latch, T latch and SR latch.

Robustness of Sequential Circuits

Abstract: Digital components play a central role in the design of complex embedded systems. These components are interconnected with other, possibly analog, devices and the physical environment. This environment cannot be entirely captured and can provide inaccurate input data to the component. It is thus important for digital components to have a robust behavior, i.e. the presence of a small change in the input sequences should not result in a drastic change in the output sequences. In this paper, we study a notion of robustness for sequential circuits. However, since sequential circuits may have parts that are naturally discontinuous (e.g., digital controllers with switching behavior), we need a flexible framework that accommodates this fact and leaves discontinuous parts of the circuit out from the robustness analysis. As a consequence, we consider sequential circuits that have their input variables partitioned into two disjoint sets: control and disturbance variables. Our contributions are (1) a definition of robustness for sequential circuits as a form of continuity with respect to disturbance variables, (2) the characterization of the exact class of sequential circuits that are robust according to our definition, (3) an algorithm to decide whether a sequential circuit is robust or not.

Robust QBF Encodings for Sequential Circuits with Applications to Verification, Debug, and Test

Abstract: Formal CAD tools operate on mathematical models describing the sequential behavior of a VLSI design. With the growing size and state-space of modern digital hardware designs, the conciseness of this mathematical model is of paramount importance in extending the scalability of those tools, provided that the compression does not come at the cost of reduced performance. Quantified Boolean Formula satisfiability (QBF) is a powerful generalization of Boolean satisfiability (SAT). It also belongs to the same complexity class as many CAD problems dealing with sequential circuits, which makes it a natural candidate for encoding such problems. This work proposes a succinct QBF encoding for modeling sequential circuit behavior. The encoding is parametrized and further compression is achieved using time-frame windowing. Comprehensive hardware constructions are used to illustrate the proposed encodings. Three notable CAD problems, namely bounded model checking, design debugging and sequential test pattern generation, are encoded as QBF instances to demonstrate the robustness and practicality of the proposed approach. Extensive experiments on OpenCore circuits show memory reductions in the order of 90 percent and demonstrate competitive runtimes compared to state-of-the-art SAT techniques. Furthermore, the number of solved instances is increased by 16 percent. Admittedly, this work encourages further research in the use of QBF in CAD for VLSI.

Analysis of soft error rates in combinational and sequential logic and implications of hardening for advanced technologies

Abstract: Previous results and models have predicted that combinational logic errors would dominate over flip-flop errors for the past few technology nodes. However, recent experimental results show very little contribution from combinational-logic soft errors to overall soft-error rates. A model that explains the soft error rates as a function of frequency is developed to account for the inconsistency in observed data. Implications for hardening against soft errors for advanced technologies are discussed.

Polymeric memory elements and logic circuits that store multiple bit states.

Abstract: The ever-increasing flow of information requires new approaches for high-density data storage (HDDS). Here, we present a novel solution that incorporates the easily accessible polymer poly(3,4-ethylenedioxythiophene) (PEDOT) with multistate memory. The electrical addressable polymer is able to store up to five different memory states, which are stable up to 20 min. The observed memory states are generated by the optical output signature of the PEDOT deposited on indium tin oxide (ITO) coated glass, upon applying specific electrical inputs. Moreover, the demonstrated platforms can be represented by a general logic circuit, which allows the construction of multistate memory, such as flip-flops and flip-flap-flop logic circuits.

Systems and methods for solving computational problems

Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.

Towards brain-inspired computing

Abstract: We present introductory considerations and analysis toward computing applications based on the recently introduced deterministic logic scheme with random spike (pulse) trains [Phys. Lett. A 373 (2009) 2338-2342]. Also, in considering the questions, "Why random?" and "Why pulses?", we show that the random pulse based scheme provides the advantages of realizing multivalued deterministic logic. Pulse trains are realized by an element called orthogonator. We discuss two different types of orthogonators, parallel (intersection-based) and serial (demultiplexer-based) orthogonators. The last one can be slower but it makes sequential logic design straightforward. We propose generating a multidimensional logic hyperspace [Physics Letters A 373 (2009) 1928-1934] by using the zero-crossing events of uncorrelated Gaussian electrical noises available in the chips. The spike trains in the hyperspace are non-overlapping, and are referred to as neuro-bits. To demonstrate this idea, we generate 3-dimensional hyperspace bases using 2 Gaussian noises as sources for neuro-bits, respectively. In such a scenario, the detection of different hyperspace basis elements may have vastly differing delays. We show that it is possible to provide an identical speed for all the hyperspace bases elements using correlated noise sources, and demonstrate this for the 2 neuro-bits situations. The key impact of this paper is to demonstrate that a logic design approach using such neuro-bits can yield a fast, low power processing and environmental variation tolerant means of designing computer circuitry. It also enables the realization of multi-valued logic, significantly increasing the complexity of computer circuits by allowing several neuro-bits to be transmitted on a single wire.

Pulse Width Allocation and Clock Skew Scheduling: Optimizing Sequential Circuits Based on Pulsed Latches

Abstract: Pulsed latches, latches driven by a brief clock pulse, offer the same convenience of timing verification and optimization as flip-flop-based circuits, while retaining the advantages of latches over flip-flops. But a pulsed latch that uses a single pulse width has a lower bound on its clock period, limiting its capacity to deal with higher frequencies or operate at lower Vdd. The limitation still exists even when clock skew scheduling is employed, since the amount of skew that can be assigned and realized is practically limited due to process variation. For the first time, we formulate the problem of allocating pulse widths, out of a small discrete number of predefined widths, and scheduling clock skews, within a predefined upper bound on skew, for optimizing pulsed latch-based sequential circuits. We then present an algorithm called PWCS_Optimize (pulse width allocation and clock skew scheduling, PWCS) to solve the problem. The allocated skews are realized through synthesis of local clock trees between pulse generators and latches, and a global clock tree between a clock source and pulse generators. Experiments with 65-nm technology demonstrate that combining a small number of different pulse widths with clock skews of up to 10% of the clock period yield the minimum achievable clock period for many benchmark circuits. The results have an average figure of merit of 0.86, where 1.0 indicates a minimum clock period, and the average reduction in area by 11%. The design flow including PWCS_Optimize, placement and routing, and synthesis of local and global clock trees is presented and assessed with example circuits.

Ultra-low power multi-threshold asynchronous circuit design

Abstract: A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL) The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction The MTNCL circuit is also capable of functioning properly under extreme supply voltage scaling down to the sub-threshold region for further power reduction Four MTNCL architectures and four MTNCL threshold gate designs offer an asynchronous logic design methodology for glitch-free, ultra-low power, and faster circuits without area overhead

Towards brain-inspired computing

Abstract: We present introductory considerations and analysis toward computing applications based on the recently introduced deterministic logic scheme with random spike (pulse) trains [Phys. Lett. A373 (2009) 2338–2342]. Also, in considering the questions, "why random?" and "why pulses?", we show that the random pulse based scheme provides the advantages of realizing multivalued deterministic logic. Pulse trains are realized by an element called orthogonator. We discuss two different types of orthogonators, parallel (intersection-based) and serial (demultiplexer-based) orthogonators. The last one can be slower but it makes sequential logic design straightforward. We propose generating a multidimensional logic hyperspace [Phys. Lett. A373 (2009) 1928–1934] by using the zero-crossing events of uncorrelated Gaussian electrical noises available in the chips. The spike trains in the hyperspace are non-overlapping, and are referred to as neuro-bits. To demonstrate this idea, we generate three-dimensional hyperspace bases using the zero-crossing events of two uncorrelated Gaussian noise sources. In such a scenario, the detection of different hyperspace basis elements may have vastly differing delays. We show that it is possible to provide an identical speed for the detection of all the hyperspace bases elements using correlated noise sources, and demonstrate this for the two neuro-bits situation. The key impact of this paper is to demonstrate that a logic design approach using such neuro-bits can yield a fast, low power and environmental variation tolerant means of designing computer circuitry. It also enables the realization of multivalued logic, and also significantly increasing the complexity of computer circuits by allowing several neuro-bits to be transmitted on a single wire.

Molecular photonic logic gates

Abstract: The possibility of performing logical operations at the molecular level is being actively investigated at present with the aim of developing molecular logic gates, which can be used in information technologies In this minireview, the design algorithm of molecular logic gates is considered and the requirements on molecular systems for use as logic gates are specified Examples of molecular logic gates performing different logical operations are given Attention is focused on all-photonic molecular logic gates, in which light is used as an input signal for transferring the system from one state to another and for reading the output signal by absorption or luminescence In addition, optoelectronic devices with light as the input signal and electric current as the output signal are briefly discussed

Soft error rate determination for nanoscale sequential logic

Abstract: We analyze the neutron induced soft error rate (SER) by modeling induced error pulse using two parameters, occurrence frequency and probability density function for the pulse width. We extend the analysis to sequential logic and latches and calculate the failures in time (FIT) rate. The analysis is developed for the available background neutron flux data, which is experimentally determined. This, along with the device characteristics, gives the induced pulse parameters. A gate-level algorithm propagates the pulse parameters through logic gates. This algorithm correctly models the logic masking of error pulses. We introduce the concept of latching window that accurately models the temporal masking by sequential elements and present an algorithm for SER analysis of sequential logic.