Showing papers on "Silicon on insulator published in 1992"

Scaling the Si MOSFET: from bulk to SOI to bulk

Abstract: Scaling the Si MOSFET is reconsidered. Requirements on subthreshold leakage control force conventional scaling to use high doping as the device dimension penetrates into the deep-submicrometer regime, leading to an undesirably large junction capacitance and degraded mobility. By studying the scaling of fully depleted SOI devices, the important concept of controlling horizontal leakage through vertical structures is highlighted. Several structural variations of conventional SOI structures are discussed in terms of a natural length scale to guide the design. The concept of vertical doping engineering can also be realized in bulk Si to obtain good subthreshold characteristics without large junction capacitance or heavy channel doping. >

SiGe thin film or SOI MOSFET and method for making the same

Abstract: A dual gate thin film or SOI MOSFET device having a sufficiently thin body thickness with one or more semiconductor channel layer(s) sandwiched by semiconductor layers having a different energy band structure to automatically confine carriers to the channel layer(s) without the need for channel grading or modulation doping. Preferred embodiments employ strained layer epitaxy having Si/SiGe/Si or SiGe/Si/SiGe semiconductor layers.

Point-contact pseudo-MOSFET for in-situ characterization of as-grown silicon-on-insulator wafers

Abstract: A pseudo-MOS transistor can be activated in as-grown silicon-on-insulator (SOI) structures without any device processing by using point-contact probes. The measurement setup for in-situ operation and typical transistor characteristics are presented. Parameters are extracted which relate to minority and majority carriers, buried oxide, and the Si-SiO/sub 2/ interface. >

The enhancement of gate-induced-drain-leakage (GIDL) current in short-channel SOI MOSFET and its application in measuring lateral bipolar current gain beta

Abstract: An off-state leakage current unique for short-channel SOI MOSFETs is reported. This off-state leakage is the amplification of gate-induced-drain-leakage current by the lateral bipolar transistor in an SOI device due to the floating body. The leakage current can be enhanced by as much as 100 times for 1/4 mu m SOI devices. This can pose severe constraints in future 0.1 mu m SOI device design. A novel technique was developed based on this mechanism to measure the lateral bipolar transistor current gain beta of SOI devices without using a body contact. >

Silicon on insulator device comprising improved substrate doping

Abstract: A silicon on insulator integrated circuit device is provided which comprises a substrate (10), a buried oxide layer (12), and an outer silicon layer (14). A buried p-layer (16) and a buried n-well region (26) are formed in order to position p-n junctions beneath n-channel and p-channel devices respectively formed in the outer silicon layer (14) outwardly from the p-layer (16) and (n)-well (26).

Method of manufacturing SOI semiconductor element

Abstract: According to a method of manufacturing an SOI semiconductor element of this invention, a structure obtained by forming a first semiconductor layer on a first insulator is prepared. A process mask is arranged on the first semiconductor layer. The process mask has a groove pattern of a predetermined size. A groove extending between the first semiconductor layer and the first insulator layer is formed by etching the first semiconductor layer on the basis of the groove pattern of the process mask to expose the first insulator layer and etching the first insulator layer to a predetermined depth. A second semiconductor layer serving as a buried electrode is formed in the groove such that a level of an upper surface of the second semiconductor layer is equal to a level of a bottom surface of the first semiconductor layer. A second insulator layer is formed on the second semiconductor layer. Crystalline growth of a semiconductor layer is performed from side surfaces of the groove to bury the groove with a monocrystalline semiconductor. A source region and a drain region are formed in the monocrystalline semiconductor buried in the groove. A gate electrode is formed on the monocrystalline semiconductor through a gate oxide film.

Dual-gate operation and volume inversion in n-channel SOI MOSFET's

Abstract: The effects of volume inversion in thin-film short-channel SOI MOSFETs and the efficacy of dual-gate operation in enhancing their device performance have been analyzed using two-dimensional device simulations and one-dimensional analytical computations. The analyses have been restricted to the strong inversion regime, which is the practically useful region of operation of the SOI MOSFETs. In this region, the analyses suggest that when compared at constant V/sub G/-V/sub T/ values, the dual-channel volume inverted devices do not offer significant current-enhancement advantage, other than that expected from the second channel, over the conventional single-channel devices for silicon thicknesses in the 0.1- mu m range. >

Method of fabricating semiconductor devices and integrated circuits using sidewall spacer technology

Abstract: The base layer of high quality spacers, such as those used on the sidewalls of the gate stack of submicron devices (e.g. MOSFETs, EPROMs), are formed as composite, multi-layered structures (22.1-22.3) of silicon oxides or of silicon oxides and silicon nitride.

Buried-oxide silicon-on-insulator structures. II. Waveguide grating couplers

Abstract: For pt.I, see ibid., vol.28, no.1, p.157-63 (1992). Grating couplers formed in buried-oxide silicon-on-insulator structures are analyzed using both a convergent Block wave approach and a simple approximate method. Strong interface reflections that occur during grating coupling can cause interference effects which result in variations in coupling efficiency and coupling length by an order of magnitude when varying grating period and film thickness parameters. Results indicate that proper coupler design is essential in order to obtain efficient coupling. >

Influence of series resistances and interface coupling on the transconductance of fully-depleted silicon-on-insulator MOSFETs

Abstract: A model is proposed to describe the variation of the transaconductance in fully-depleted silicon on insulator MOSFETs as a function of the front/back gate biases, channel length and series resistances. The influence of series resistances on the static characteristics of short-channel transistors depends on the region of operation, via the front and back gate voltages, and is a maximum when both interfaces are inverted. Simple analytical expressions explain the gradual deformation of the transconductance curve and the lowering of the transconductance peak with increasing series resistances. The model is experimentally verified by associating external resistors to the transistor. It is shown that a major consequence of X-ray irradiations in short-channel SIMOX MOSFETs is the trapping of positive charges in the buried oxide, which causes activation of interface coupling effects and enhanced influence of series resistances.

Method of fabricating SOI wafer with SiGe as an etchback film in a BESOI process

Abstract: An SOI wafer is formed having a silicon-germanium layer between the epitaxial layer of the device and the insulative layer. The process includes bonding a second substrate to a silicon-germanium layer on a first substrate by an intermediate insulative layer. The first substrate is removed down to the silicon-germanium layer and the silicon layer is epitaxially formed on the silicon-germanium layer.

Effect of microscale thermal conduction on the packing limit of silicon-on-insulator electronic devices

Abstract: It is pointed out that silicon-on-insulator (SOI) electronics have a buried silicon dioxide layer which inhibits device cooling and reduces the thermal packing limit, the largest number of devices per unit substrate area for which the device operating temperature is acceptably low. Thermal analysis yields the packing limit of SOI MOSFET devices in terms of the device power and the limit on the channel temperature. Thermal conduction is microscale if it is significantly reduced by the boundary scattering of heat carriers, electrons in aluminum, and phonons in silicon. If microscale effects are not considered, the packing limit is overpredicted by 22% for a substrate temperature of 300 K and 100% for substrate temperature of 77 K. >

Semiconductor substrate having a soi structure and method of producing the same

Abstract: A semiconductor substrate is formed by bonding wafers together by heat-treatment without causing the substrate to be thermally damaged to have thermal strain, separation, cracks, etc. due to a difference in the thermal expansion coefficients of the wafers. Particularly, a semiconductor substrate having an SOI structure with a silicon film thin enough to allow various integrated circuits or TFL-LCD to be formed, is produced. After wafers are bonded temporarily in a low temperature range, one of the wafers is made thin by chemical treatment, then the wafers are bonded fully by heat-treatment in a temperature range (where the thermal expansion coefficients of the wafer are not affected) higher than the above low temperature range, and then said one wafer can be made thinner by mechanical grinding or polishing mechano-chemically. Even if a semiconductor substrate is formed by sticking a silicon wafer and a quartz wafer together, damages that will be caused thermally due to thermal expansion can be prevented, and a film can be easily obtained which is sufficiently thin as required for forming various integrated circuits or TFT-LCD or the like.

Wafer bonding technology for silicon-on-insulator applications: a review

Abstract: School of Engineering, Duke University, Durham, North Carolina, 27706. The status of wafer bonding technology especially for silicon-on-insulator (SOI) materials is reviewed. General advantages of wafer bonding as well as specific problems of wafer bonding, such as interface bubble formation, and solutions for these problems are discussed. The specific requirements for SOI materials in terms of SOI layer thickness and the appropriate thinning procedures are dealt with. Interface properties such as bonding strength and electrical properties are also reviewed. Various device results are mentioned.

Method of forming an SOI structure with a DRAM

Abstract: of EP0537677The present invention concerns a method of manufacturing a SOI substrate of forming a thin film of a silicon layer on an insulator substrate by bonding a substrate, wherein the method comprises successively: a step of forming an etching stopping layer on the surface of a silicon substrate, a step of forming an epitaxially grown silicon layer on said etching stopping layer, a step of bonding said silicon substrate formed with said silicon layer with another substrate as the insulator substrate, a step of grinding said silicon substrate from the rear face and etching it till said etching stopping layer is exposed and a step of removing said etching stopping layer.

Process for making thin film silicon-on-insulator wafers employing wafer bonding and wafer thinning

Abstract: A very thin silicon film SOI device can be made utilizing a bond and etch-back process. In the presently claimed invention, boron dopant is introduced into a surface of a silicon device wafer and the doped surface is bonded onto another silicon wafer at an oxide surface. The device wafer is thinned by etching down to the doped region and, by subsequent annealing in hydrogen, boron is diffused out of the silicon surface layer to produce very thin SOI films.

SOI BICMOS process

Abstract: This invention is an SOI BICMOS process which uses oxygen implanted wafers as the starting substrate. The bipolar transistor is constructed in two stacked epitaxial layers on the surface of the oxygen implanted substrate. A buried collector is formed in the first epitaxial layer that is also used for the CMOS transistors. The buried collector minimizes the collector resistance. Selective epitaxial silicon is then grown over the first epitaxial layer and is used to form the tanks for the bipolar transistors. An oxide layer is formed over the base to serve as an insulator between the emitter poly and the extrinsic base, and also as an etch stop for the emitter etch. The emitter is formed of a polysilicon layer which is deposited through an opening in the oxide layer such that the polysilicon layer contacts the epitaxial layer and overlaps the oxide layer.

Silicon on Insulator Structures Obtained by Epitaxial Growth of Silicon over Porous Silicon

Abstract: Epitaxial silicon films are obtained by low temperature chemical vapor deposition on porous silicon layers (PSL). The PSL are formed on lightly and highly boron doped silicon substrates. In the case of lightly doped substrates, the epitaxial films exhibit a large defect density (10 10 cm -2 ). It is shown that this defect density can be reduced by a 10 2 to 10 3 factor through the use of silicon channeled implantation and subsequent thermal annealing. On the other hand, when the epitaxial growth is performed on PSL formed from highly doped boron substrates, the epitaxial quality of the resulting films is equivalent to the homoepitaxy of silicon on bare silicon

SOI technology for high-temperature applications

Abstract: This work investigates and demonstrates the potential of Silicon-On-Insulator (SOI) MOSFETs for high-temperature analog and digital applications. The small area of junctions in SOI/MOS devices reduces the high-temperature leakage currents by as much as 3 to 4 orders of magnitude over regular (bulk) MOS devices. The threshold voltage variation with temperature is 2 to 3 times smaller than in bulk devices, and the output conductance of SOI MOSFETs actually improves as temperature is increased. These properties enable the fabrication of digital and analog SOI/CMOS circuits operating up to over 300 degrees C with little performance degradation. This paper describes the high-temperature performances of small SOI/CMOS circuit blocks such as static and dynamic logic gates, frequency dividers, and operational amplifiers. >

Novel polysilicon/TiN stacked-gate structure for fully-depleted SOI/CMOS

Abstract: Fully-depleted SOI/CMOS transistors were fabricated using titanium-nitride (TiN) gates with near midgap work-function in order to optimize the p- and n-channel threshold voltages for operation at low supply voltage. To simplify the process as well as to minimize the strain, a novel gate structure was used in which a thick polysilicon (300 nm) was stacked on a thin TiN layer ( >

Semiconductor integrated circuit device with plural gates and plural passive devices

Abstract: In a sea-of-gate structure gate array in which a plurality of logic gates are arrayed on a semiconductor chip, resistance devices or capacitive devices are formed without reducing the gate scale to form analog components to render the gate array into a hybrid gate array including the analog components. A number of MOS transistors to be formed without vacancies on the chip surface are formed in a thin silicon section on an insulating layer 15. The logic gates arrayed on the chip is of the SOI structure. Below the insulating layer 15, a lower capacitor electrode 12, a dielectric film 13, an upper capacitor electrode 14 and a resistance element are formed so as to be buried in an insulating film 11 on a supporting substrate 10 or in an insulating substrate. The capacitor and the resistance are led to the chip surface by means of a contact hole 23 provided in the insulating layer 15. A grinding stop 16 is formed in the insulating layer 15. The thin silicon section of the SOI structure is produced by grinding the substrate.

Measurement and modeling of self-heating effects in SOI nMOSFETs

Abstract: Self-heating effects in SOI nMOSFETs are measured and modeled. Temperature rises in excess of 100 K are observed for SOI devices under static operating conditions. The measured temperature rise agrees well with the predictions of the analytical model, and is found to be a function of the silicon thickness, buried oxide thickness, and channel-metal contact separation. This work facilitates the optimization of these dimensions to improve device cooling, and provides the foundation for the calculation of circuit parameters for dynamic operation from static device characterization data. Self-heating effects do not appear to limit SOI circuit performance, but might influence device design for 0.25 mu m technologies and below. >

Twin-MOSFET structure for suppression of kink and parasitic bipolar effects in SOI MOSFETs at room and liquid helium temperatures

Abstract: A twin-MOSFET structure is proposed for suppression of the kink and parasitic bipolar effects in SOI MOS transistors. It is also an attractive candidate to provide satisfactory linear device operation at liquid He temperature. The device consists of two transistors in series with a common gate but it operates as a single transistor. Kink effect can be confined to the one “slave” transistor while the other “master” transistor can be kept free from the kink effect. If the gate length of the master transistor is larger than that of the slave one, the kink-free master transistor dominates the overall output characteristics of the device. As a consequence, the kink effect is suppressed in the overall output characteristics of the device. Furthermore, the parasitic bipolar effect in SOI MOSFETs is also significantly reduced and the saturation drain output impedance as well as the output breakdown characteristics are drastically improved. Kink-free and very flat output characteristics are obtained at both room and liquid He (4.2 K) temperatures.

SOI diaphgram sensor

Abstract: The present invention relates to the fabrication of diaphragm pressure sensors utilizing silicon-on-insulator technology where recrystallized silicon forms a diaphragm which incorporates electronic devices used in monitoring pressure. The diaphragm is alternatively comprised of a silicon nitride having the necessary mechanical properties with a recrystallized silicon layer positioned thereon to provide sensor electronics.

Long-channel silicon-on-insulator MOSFET theory

Abstract: Based on the procedure of Pierret and Shields [1, Solid-St. Electron. 26 , 143, 1983] for the long-channel bulk MOSFET, a new single-integral expression is obtained to describe the current-voltage characteristics for the silicon-on-insulator (SOI) MOSFET. This expression is valid for: any degree of inversion, all back-gate bias conditions and any semiconductor film thickness. Our single-integral expression, applied to a given back-gate bias condition and using the appropriate approximations, can be simplified to the results of the previous models.

Method for fabrication of semiconductor device

Abstract: This invention is directed to prevent step breakage and short-circuit of wires resulting from steps of isolation trenches formed in an SOI substrate. An oxide film for a pad is formed on a main plane of an SOI layer formed on an insulating substrate and furthermore, a silicon nitride film and an SiO2 film are sequentially formed. Thereafter, isolation trenches reaching the insulating substrate are formed by RIE using the SiO2 film as the mask. An insulating film is then formed on the inner wall of the isolation grooves by thermal oxidation, and polycrystalline silicon is filled into the insolation trenches. This polycrystalline silicon is etched back while control is made so that the upper end of polycrystalline silicon inside the isolation trenches is above the upper end of the silicon nitride film, and the excessive polycrystalline silicon deposited on the substrate surface is removed. Next, polycrystalline silicon inside the isolation trenches and the silicon nitride film are used as an etching stopper to etch and remove the SiO2 film used as the mask at the time of the formation of the isolation trenches. Since this etching and removal of the SiO2 film used as the mask is carried out after polycrystalline silicon is filled into the isolation trenches, the oxide film for isolating the substrates inside the SOI substrate is not etched when the mask is removed. When the masking SiO2 film is etched and removed, polycrystalline silicon and the silicon nitride film inside the isolation trenches function as the etching stopper, and the oxide film for the pad as the lower layer and the insulating film formed on the inner wall of the trenches are prevented from being etched, and flatness in the trench portions is not lost.

Self-heating in high performance bipolar transistors fabricated on SOI substrates

Abstract: The effects of self-heating on the characteristics of bipolar transistors fabricated on silicon-on-insulator (SOI) substrates are discussed through measurements and simulations. It is shown that the SOI substrate's buried oxide affects the thermal characteristics of the transistor. A three fold increase in thermal resistivity is observed on transistors fabricated on SOI substrates over identical transistors fabricated on regular silicon substrates. Moreover, thermal gradients within the device footprint are also discussed and evaluated both experimentally and using MEDICI simulations. Finally, a simple thermal model is presented which predicts transistor characteristics with good accuracy. >

XFCB: a high speed complementary bipolar process on bonded SOI

Abstract: A fabrication process was developed to obtain full, dielectrically isolated complementary bipolar transistors. Direct-wafer-bonding silicon-on-insulator and deep-trench-isolation technologies were used. Polysilicon was used as the emitter for both NPN and PNP transistors. A single layer of polysilicon was used to fabricate both transistor types. The process is characterized by a 12 V breakdown and yields transistors with a cutoff frequency of 4.5 GHz and 2.5 GHz for the NPN and PNP devices, respectively. >

Self-aligned silicide technology for ultra-thin SIMOX MOSFETs

Abstract: The salicide technology using rapid thermal annealing was applied to MOSFETs on thin-film SOI. Since the SOI film was limited to a thickness of less than 100 nm, the silicidation reaction between Ti and Si atoms on the SOI surface exhibited new features that depended on the initial thickness of the deposited Ti. There was an optimum thickness of as-deposited Ti on silicidation due to the restricted thickness of the Si layer. Beyond the optimum point, the region adjacent to the silicided Si layer works as a Si source to assure stoichiometric TiSi/sub 2/. The subthreshold slopes and carrier mobilities were not changed by the salicide process. Junction leakage characteristics were slightly degraded; however, the change was small enough for device application. The influence on AC characteristics was well demonstrated for a high-speed CMOS ring oscillator with a gate length of 0.7 mu m. The minimum delay time/stage was 46 ps/stage at 5 V. This gives 1.8 times higher speed operation than the controlled bulk CMOS ring oscillators with the same design rule. >

SOI technology for high-temperature applications

Abstract: This work investigates and demonstrates the potential of Silicon-On-Insulator (SOI) MOSFETs for high-temperature analog and digital applications. The small area of junctions in SOI/MOS devices reduces the high-temperature leakage currents by as much as 3 to 4 orders of magnitude over regular (bulk) MOS devices. The threshold voltage variation with temperature is 2 to 3 times smaller than in bulk devices, and the output conductance of SOI MOSFETs actually improves as temperature is increased. These properties enable the fabrication of digital and analog SOI/CMOS circuits operating up to over 300°C with little performance degradation. This paper describes the high-temperature performances of small SOI/CMOS circuit blocks such as static and dynamic logic gates, frequency dividers, and operational amplifiers