Showing papers on "Strained silicon published in 1988"

Method of fabricating back surface point contact solar cells

Abstract: A back surface point contact silicon solar cell having improved characteristics is fabricated by hydrogenating a silicon-silicon oxide interface where hydrogen atoms are diffused through silicon nitride and silicon oxide passivating layers on the surface of a silicon substrate. In carrying out the hydrogenation, the substrate and passivation layers are placed in a hydrogen atomsphere at an elevated temperature of at least 900° C. whereby hydrogen atoms diffuse through the two passivation layers. Self-alignment techniques are employed in forming small-geometry doped regions in the surface of the silicon substrate for the p-n junctions of the solar cell. Openings are formed through the passivation layers to expose first surface areas on the substrate, and a doped silicon oxide layer is then formed over the passivation layers and on the exposed surface areas. Portions of the first doped layer on the two passivation layers are removed and then second portions of the two passivation layers are removed, thereby exposing second surface areas. A second doped silicon oxide layer is then formed over the passivation layers and on the second exposed surface areas. Dopants from the two doped silicon oxide layers are then diffused into the first and second surface layers to form p and n diffused regions in the surface of the substrate. Thereafter, the first and second doped silicon oxide layers are removed by a preferential etchant which does not remove the silicon nitride layer, thereby exposing the first and second surface areas. A two-level metal interconnect structure is then formed for separately contacting the first surface areas and the second surface areas.

Electrically active point defects in amorphous silicon nitride: An illumination and charge injection study

Abstract: We observe a strong correlation between changes in the density of paramagnetic silicon ‘‘dangling‐bond’’ centers and changes in the space‐charge density in amorphous silicon nitride films subjected alternately to illumination and both positive‐ and negative‐charge injection. We demonstrate that ultraviolet illumination annihilates space charge and creates stable paramagnetic centers in silicon nitride. These centers can be passivated with a 1‐h anneal at 250 °C. Our results provide the first direct experimental evidence associating a specific point defect with the trapping phenomena in amorphous silicon nitride. We also demonstrate both directly and for the first time the amphoteric nature of the silicon nitride dangling‐bond center. Furthermore, our ability to cycle the defect between its paramagnetic neutral state and both its charged diamagnetic states suggests that the optical generation of dangling bonds in amorphous silicon nitride involves no complex structural rearrangement, but simply changes in ...

Silicon nitride in electronics

Abstract: Introduction. 1. General Description of the Processes of Deposition of Silicon Nitride Films from a Gas Phase. Thermodynamic analysis of the silicon nitride CVD processes. Kinetic model of the deposition processes from a gas phase. References. 2. Methods of Synthesis. Direct nitridation of silicon. Deposition from the silane-containing gas phase. Deposition from the gas phase containing silicon tetrahalogens and silane halides. Synthesis of oxynitride silicon films. Synthesis of films by the methods of plasm- and photochemistry. References. 3. Modelling of Low-Pressure CVD Processes. General characteristics of the LPCVD. Thermal conditions of low-pressure reactors. Film thickness uniformity problem. Two groups of processes. Model of the processes with a limiting heterogeneous stage. Model of the processes with a limiting homogeneous stage. Summary. References. 4. Structure and Chemical Composition of Silicon Nitride. Structure of silicon nitride and oxynitride films. Chemical composition of silicon nitride. Chemical bond in silicon nitride. References. 5. Physical-Chemical Transformations in Silicon Nitride Films. Crystallization of silicon nitride and oxynitride films. Variation of the chemical composition of silicon nitride films under thermal treatment in different gaseous ambiences. Diffusion of impurities in silicon nitride films. Dissolution of silicon nitride films. References. 6. Electronic Structure and Optical Properties of Silicon Nitride. Silicon nitride structure of variable composition according to data of electron and vibrational spectroscopy. Electronic structure of a-Si 3 N 4 . Electronic structure of a-SiN x O y and SiN x . Optical properties of silicon nitride. Energy diagram of the MNS structure. Optical properties of a-SiN x O y and energy diagram of the Si-SiN x O y -Al structures. Red shift of the absorption edge in SiN x and irradiated Si 3 N 4 . Models of deep centres in a-Si 3 N 4 . References. 7. Electrophysical Properties. General description of electronic processes in amorphous silicon nitride. Polarization of silicon nitride layers. Depolarization of silicon nitride layers. Silicon nitride conduction. Recombination and diffusion of charge carriers in silicon nitride. Complex conductivity and noises of silicon nitride. Degradation of electrophysical properties of silicon nitride. Properties of nonstoichiometric silicon nitride. References. 8. Application of Silicon Nitride Films in Microelectronics. LOCOS process. Silicon nitride as a mask in diffusion. Silicon nitride films in electrically programmed read only memory (EPROM). Use of silicon nitride films for stabilization of MIS transistors. Ion-selective MNOS-transistors as indicators of pH of solutions and hydrogen impurities in gases. Films of silicon nitride and oxynitride as elements of the constructions of integrated optics. Optical MD on MNOS-structures. Increase of the radiative stability of MIS devices.

Thin film silicon semiconductor device and process for producing thereof

Abstract: A thin film silicon semiconductor device provided on a substrate (12) according to the present invention comprises a thin polycrystalline silicon film (14) having a lattice constant smaller than that of a silicon single crystal and a small crystal grain size This thin polycrystalline silicon film can be obtained by depositing a thin amorphous silicon film in an inert gas having a pressure of 35 Pa or lower by a sputtering deposition method and annealing the thin amorphous silicon film for a short time of 10 seconds or less to effect polycrystallization thereof A thin film silicon semiconductor device comprising such a thin polycrystalline silicon film having a small lattice constant has excellent characteristics including a carrier mobility of 100 cm²/V·s or higher

Nature of the dominant deep trap in amorphous silicon nitride.

Abstract: We observe a strong correlation between changes in the density of paramagnetic silicon-``dangling-bond'' centers and changes in the space-charge density in amorphous silicon nitride films subjected alternately to positive and negative charge injection and optical illumination. Our results provide, for the first time, direct experimental evidence associating a specific point defect with the trapping phenomena in amorphous silicon nitride. We also demonstrate both directly and for the first time the amphoteric nature of the silicon nitride silicon-dangling-bond center.

Method for growing single crystalline silicon with intermediate bonding agent and combined thermal and photolytic activation

Abstract: A method is provided for epitaxially growing single crystalline silicon on a silicon substrate (10) from a silicon-bearing gas (26) at a temperature below the pyrolytic threshold of the gas and at temperatures below those normally required for epitaxial growth. An oxidized silicon substrate (10) is fluorinated (equation 2, FIG. 2) to replace the silicon-oxide layer with an adsorbed fluorinated layer. The substrate is placed in a laser photo-CVD reactor chamber (20), the chamber is evacuated to a sub-UHV level of 10 -3 to 10 -7 Torr, the substrate is heated to 570° C., hydrogen gas (24) is introduced into the chamber, and excimer pulsed ultraviolet laser radiation (32 from laser 12) is applied through the hydrogen gas to impinge the wafer substrate. The combined effect removes regrown native oxide and removes the adsorbed fluorinated layer and breaks the hydrogen into atomic hydrogen such that the latter bonds with the silicon in the substrate and replaces the adsorbed fluorinated layer with silicon-hydrogen bonds (equation 4, FIG. 2). The substrate is maintained at 570° C. and disilane is introduced into the chamber, and excimer pulsed ultraviolet laser radiation is applied through the disilane gas to impinge the wafer substrate. The combined effect breaks the silicon-hydrogen bond and decomposes the disilane to silane and an unstable intermediate SiH z which decomposes to hydrogen and atomic silicon (equation 5, FIG. 2), which atomic silicon bonds to the now unbonded silicon in the substrate to epitaxially grow single crystalline silicon.

Semiconductor device having a two-layer gate structure

Abstract: A semiconductor device is disclosed, which comprises source and drain regions formed in a spaced-apart relation to each other on an isolated semiconductor substrate surface, a first conductive layer formed over a channel region between the source and drain regions via a gate insulating film and serving as a floating gate electrode, a two-layer insulating layer formed on the first conductive layer and consisting of a silicon oxynitride film and a silicon oxide film, and a second conductive layer formed on the two-layer insulating layer and serving as a control gate electrode. In the semiconductor device of this structure, the silicon oxynitride film traps fewer electrons, and electrons are infrequently trapped at the time of data erasing, so that data-erasing characteristics can be improved. Further, since fewer electrons are trapped, unlike the prior art insulating layer utilizing a silicon nitride film, there is no need for providing any silicon oxide film on each side, and with the two-layer structure consisting of the silicon oxynitride film and a silicon oxide film it is possible to obtain sufficient insulation and film thickness reduction.

Neutral E’ centers in microwave downstream plasma‐enhanced chemical‐vapor‐deposited silicon dioxide

Abstract: We have utilized electron spin resonance and capacitance versus voltage measurements to study E’ centers generated by the photoemission of electrons into silicon dioxide films prepared by plasma‐enhanced chemical vapor deposition (PECVD). The oxides were deposited on crystalline silicon substrates downstream from a microwave discharge. The E’ center is an unpaired electron in a nonbonding sp3 hybrid orbital on a silicon bonded to three oxygen atoms. In conventional thermal SiO2 films on silicon, E’ centers are the dominant deep hole traps. However, the E’ centers generated in the PECVD oxides are generated by electron injection into the oxide and are almost certainly electrically neutral. Our results unequivocally demonstrate fundamental differences in the point defects in thermally grown SiO2 on silicon and PECVD oxides.

Method for fabricating a semiconductor integrated circuit structure having a submicrometer length device element

Abstract: A method for fabricating a semiconductor integrated circuit structure having a submicrometer length device element is described wherein a surface isolation pattern (12) is formed in a semiconductor substrate (10) to define regions which are designated to contain devices. A first insulating compound layer (16.1,2,3) is formed on the surface of the semiconductor substrate which is designated to be in part the gate dielectric. Subsequently, a polycrystalline silicon layer (20) is deposited onto said compound layer. Polycrystalline silicon layer (20) is heavily doped by phosphorus ion implantation and annealed below about 850°C. Polycrystalline silicon portions are delineated by photolithography and dry etching. Dry etching is carried out in SF₆/Cl₂/ He at a low power density of about 0.1 to 0.3 W/cm². The remaining portions of polycrystalline silicon layer (20) are subjected to a thermal oxidation at a temperature of about 800°C during which controllable quantities of the poly­crystalline silicon are consumed. After removal of the thermally grown oxide (26) polycrystalline silicon portions are obtained with length and thickness dimensions reduced by the desired amount. If polycrystalline silicon portions (20) are to be reduced only in length, rather than both in length and thickness, the horizontal surfaces of these portions have to be protected during oxidation by a cap. The cap may consist of a several nm thick silicon nitride layer which is arranged on a silicon dioxide stress-­relieve layer. The method is particularly useful in forming a sub­micrometer length gate electrode of a field effect transistor.

Formation of submicron silicon‐on‐insulator structures by lateral oxidation of substrate‐silicon islands

Abstract: Fully isolated islands have been formed in silicon using selective, lateral thermal oxidation at the base of 250‐nm‐wide structures. The final structure consists of substrate silicon on thermal oxide on substrate silicon. The process begins with the definition of 250‐nm‐wide islands that are capped on the top and sidewall with a silicon dioxide/silicon nitride oxidation mask. The structure is then isotropically or anisotropically recess etched and thermally oxidized to produce isolated silicon islands. Our experiments show that the quality of the silicon‐on‐insulator structure depends on the oxidation mask, the island dimension, the profile of the recess etch, and the oxidation time and temperature. The degree of isolation can be tailored by controlling the lateral oxidation of the filament connecting the island to the underlying substrate. By this technique we have formed silicon filaments of 10 to 100 nm in width.

Nitride cantilevers with single crystal silicon tips

Abstract: A nitride cantilever is formed with an integral conical silicon tip at the free end thereof. A top layer of silicon dioxide is patterned into a tip mask on a doped or epitaxial silicon layer in a silicon substrate. Photoresist is spun on the silicon substrate and patterned and the silicon is etched to define a cantilever pattern in the substrate with the tip mask positioned to be near the free end of a nitride cantilever to be subsequently formed. A bottom layer of silicon dioxide is formed on the silicon substrate and then patterned and etched to define a masking aperture on the bottom silicon dioxide layer. The bottom of the silicon substrate is anisotropically etched through the masking aperture and the etch stops at the doped silicon layer. Alternatively, electrochemical etching is done by applying an electric potential across the P-N junction between the doped silicon layer and the appropriately-doped substrate. This releases the free end of the doped silicon layer from the silicon substrate. The anisotropic etch preferentially etches all of the crystal planes of the silicon substrate except the (111) planes to leave a silicon base from which extends the silicon surface layer as a cantilever. A nitride layer is then formed on the silicon substrate and dry etched from the top surface of the doped silicon surface layer to form a nitride cantilever on the bottom of the silicon substrate. The doped silicon layer is etched away while the tip mask helps to form a pointed silicon tip near the free end of the nitride cantilever. A microfabricated cantilever includes a (100) silicon base having a (111) oblique side. A nitride layer is formed over the (111) oblique side of the silicon base and extends outwardly from the top surface of the silicon base to form a nitride cantilever having one end fixed to the silicon base and having a free end. On the free end is fixed a single-crystal sharp conical silicon tip which extends upwardly.

Producing a compound semiconductor device on an oxygen implanted silicon substrate

Abstract: A production method for producing a semiconductor device by growing a crystalline compound semiconductor on a monocrystalline silicon substrate is comprised of a step for forming a transition domain varying from a monocrystalline silicon layer to a polycrystalline silicon layer in the silicon substrate by implanting oxygen ions into the silicon substrate and annealing the silicon substrate and a step for depositing a compound semiconductor layer on the silicon substrate.

Heterojunction bipolar transistor with SiGe

Abstract: A heterojunction bipolar transistor has an emitter which comprises an expitaxial layer of silicon grown on a silicon and germanium base layer. The active region of the transistor comprises a semiconductor having a silicon/silicon and germanium strained lattice and the silicon and germanium base layer is grown on a silicon substrate while maintaining commensurate growth. The lattice strain is such as to produce a predetermined valence band offset at the emitter/base junction. The mobility in the base is also enhanced over that of an unstrained alloy of the same composition.

Method for forming a silicon membrane with controlled stress

Abstract: A method for fabricating a silicon membrane with predetermined stress characteristics. A silicon substrate is doped to create a doped layer as thick as the desired thickness of the membrane. Stress within the doped layer is controlled by selecting the dopant based on its atomic diameter relative to silicon and controlling both the total concentration and concentration profile of the dopant. The membrane is then formed by electrochemically etching away the substrate beneath the doped layer.

LCMOS displays fabricated with implant treated silicon wafers

Abstract: An improved LCMOS display device employing a silicon-on-insulator (SOI) substrate (41) having an epitaxial silicon layer (15) lying over an implant-generated dielectric layer (13). MOS device and capacitor elements (17, 19, 21) used to activate the display are formed and interconnected in the epitaxial silicon (15). The implant-generated dielectric layer (13) and underlying silicon substrate (41) also serve as capacitor elements, thereby simplifying the structure and fabrication of the display device and providing improved operation through improved isolation of the MOS device elements formed in the epitaxial silicon (15) from the substrate (41).

Vacuum emission of hot electrons from silicon dioxide at low temperatures

Abstract: Low temperature (to 83 K) vacuum emission of hot electrons from silicon dioxide films is reported. This technique is specifically used to study the temperature dependence of the electronic distributions emerging into vacuum from very thin (50–60 A) oxide layers where a significant number of the electrons have traveled through the insulator ballistically. The measured energy distributions of the emerging carriers are shown to reflect the temperature‐dependence of the distribution of the electron source in the silicon substrate at the abrupt interface with the silicon dioxide layer, particularly the Fermi tail, and possibly quantized levels in the silicon accumulation layer. The other features in the electron distributions are shown to be due to single phonon scattering of ballistic electrons in the silicon dioxide layer. Additionally, it is shown that as the oxide thickness is increased, the distribution broadens into its steady‐state characteristic, showing very little temperature dependence. All data are...

Semiconductor device with multilayer silicon oxide silicon nitride dielectric

Abstract: A solid state device includes a transistor (A) and a capacitor (B). The capacitor is defined by a lower polycrystalline silicon layer or electrode (20), multiple dielectric layers (22), and an upper polycrystalline silicon layer or electrode (30). The dielectric layers are formed by vapor depositing a 3.6-18.6 nm thick layer of silicon nitride on the lower polycrystalline layer. Thicker silicon nitride layers increase the failure rate and decrease the capacitance (FIG. 8). More specifically, the silicon nitride layer is deposited on a thin, about 1 nm, oxidized film or surface (24) of the polycrystalline silicon layer. The silicon nitride layer is oxidized forming a silicon dioxide layer (28) until the silicon nitride layer is only about 3 nm thick. This forms on oxide layer that is 1-8.4 nm thick. If the silicon nitride layer is reduced below 3 nm, the polycrystalline silicon tends to oxidize rapidly reducing capacitance and increasing failure (FIG. 8).

Silicon carbide barrier between silicon substrate and metal layer

Abstract: A silicon carbide layer between a silicon substrate or layer and a metal layer because silicon carbide has many properties similar to those of silicon, has a very slow diffusion rate of a metal through the silicon carbide, or prevents a diffusion of a metal into the silicon, and can be deposited by CVD, which has an advantage of a good coverage over a step portion such as a contact window.

Semiconductor device having Schottky barrier between metal silicide and silicon

Abstract: A semiconductor device having a Schottky barrier junction formed between a metal silicide layer and a monocrystalline silicon layer is disclosed. A polycrystalline silicon layer is formed so as to make a contact with a portion of the surface of the monocrystalline silicon layer and is further elongated over an insulation film which selectively covers the surface of the monocrystalline silicon layer. The metal silicide layer has a first portion making contact with the monocrystalline silicon layer to form the Schottky barrier junction and further has a second portion covering the polycrystalline silicon layer. The second portion of the metal silicide layer and the polycrystalline silicon layer are employed for interconnect the Schottky barrier junction to another or other circuit elements.

Gating of germanium surfaces using pseudomorphic silicon interlayers

Abstract: A novel insulator structure for gating of germanium surfaces has been developed. The structure consists of a very thin (on the order of 10 A) pseudomorphic silicon layer deposited on the germanium surface prior to deposition of a silicon dioxide insulating layer. Both the silicon and silicon dioxide layers were deposited at low temperature by remote plasma‐enhanced chemical vapor deposition. Low interface state densities and surface inversion have been obtained for both n‐ and p‐type germanium substrates. X‐ray photoelectron spectroscopy and ion scattering spectroscopy analysis indicate that the thin pseudomorphic silicon layer provides complete silicon coverage of the germanium surface. The silicon layer protects the germanium surface from undesirable oxidation during the silicon dioxide deposition. The electrical properties of germanium metal‐insulator‐semiconductor structures which incorporated the silicon interlayer were much improved compared to structures in which the silicon dioxide was deposited d...

Epitaxial process for silicon on insulator structure

Abstract: The present invention provides products and methods of forming an epitaxial silicon layer on an implanted buried insulator silicon on insulator structure (10). A silicon film (16) is pre-treated to remove residual oxide and surface damage layers, but in such a way as to not damage the silicon film (16) or insulating layer (14) below the silicon film (16). A layer of amorphous silicon (18) is formed on the silicon film (16) in processes to avoid formation of polycrystalline silicon, and also to avoid damage to the silicon film (16). The layer of amorphous silicon (18) is annealed to form an epitaxial layer of single crystalline silicon (20).

A new silicon-on-glass process for integrated sensors

Abstract: A process is reported for the formation of high-performance thin single-crystal silicon films on glass substrates. The process utilizes the electrostatic bonding of a silicon wafer to glass and subsequent etching of the silicon to form films having thickness controlled from less than 2 mu m to over 20 mu m. The use of Corning 1729 glass substrates yields an excellent thermal expansion match to the silicon film and allows the use of postbond processing temperatures for the films of as high as 800 degrees C, allowing the formation of both MOS and bipolar device structures. Thus, integrated circuitry can be incorporated in dissolved-wafer sensing structures. A variety of related processes are also possible where some or all of the silicon device processing is performed at high temperature before bonding to the glass. >

Planar tungsten interconnect with implanted silicon

Abstract: A planar interconnect using selective deposition of a refractory metal such as tungsten into oxide channels is disclosed. A layer of silicon dioxide as thick as the desired tungsten interconnect is placed on the surface of a substrate such as an integrated circuit wafer. Thereafter, a layer of silicon nitride about 100 nm thick is formed on the silicon dioxide. Channels are formed in the silicon dioxide by patterning and etching the composite dielectric layers. After the photoresist is removed, silicon or tungsten atoms at 40 KeV are implanted in the silicon dioxide channels, the silicon nitride acting as a mask. Typically, a dosage as high as 1×10 17 cm -2 is used. The silicon or tungsten implant allows seeding of the tungsten or other retractory metal. The silicon nitride mask is selectively removed by a hot phosphoric acid solution, and a metal film is then selectively deposited to fill the channels in the silicon dioxide layer, which then forms a level of interconnects. The process is repeated to form vias and subsequent levels of interconnects.

Method of direct write desposition of a conductor on a semiconductor

Abstract: An improved method of patterning a conductive interconnect on a semiconductor element is disclosed. A catalytic layer of, for example, amorphous silicon is deposited on a semiconductor element. The areas over which a conductive pattern is to be formed is activated by directing a focused laser beam onto the amorphous silicon to form crystallized silicon. The amorphous silicon is then etched away after which a conductive material such as a metal is deposited on the activated crystallized silicon.

Semiconductor device having polycrystalline silicon resistor

Abstract: A semiconductor device having a silicon resistor element is disclosed. The silicon resistor element includes a first polycrystalline silicon film containing oxygen atoms with a low density, and a second polycrystalline silicon film disposed on the first polycrystalline silicon film and containing oxygen atoms with a high density. A silicon oxide film converted from polycrystalline silicon is attached to the top surface of the second polycrystalline silicon film.

Chemical vapor deposition of a silicon nitride layer with an excellent interface by NH3 plasma treatment

Abstract: A new metal‐insulator‐semiconductor field‐effect transistor (MISFET) fabrication technology has been developed by using a silicon nitride insulator. MISFET’s with high field‐effect mobility were obtained by exposing a silicon surface to a NH3 plasma before silicon nitride (SiNx) deposition as a gate insulator in a rf plasma. An Auger spectrum showed possible nitridation of silicon by NH3 plasma treatment.

Properties of buried insulating layers in silicon formed by high dose implantation at 60 keV

Abstract: Buried silicon nitride and oxynitride layers were formed in silicon by ion beam synthesis at 60 keV. In all cases monocrystalline silicon top layers were found already after implantation. Their defect density is reduced strongly after annealing at 1200°C which leads also to narrowing of the interregions silicon/compound layer. Silicon oxynitride remains amorphous after annealing. The electrical resistivity of the buried layer is in the range of 1015–1016 Ωcm. The quality of the layer systems with silicon oxynitride depends on the implantation sequence of the species. The long range order of polycrystalline silicon nitride may be strongly reduced by ion implantation.

Method for manufacturing poly-crystal sillicon having high resistance

Abstract: Method for manufacturing polycrystalline silicon having high resistance, having a first step for depositing a polycrystalline silicon layer for a resistor area over a silicon semiconductor substrate; a second step for growing a first thermal oxide layer having a first specified depth over the polycrystalline silicon layer, ion-implanting with the nitrogen thereon, and growing a second thermal oxide layer having a second specified depth on the ion-implanted layer; a third step for forming a resistor pattern of the polycrystalline silicon with a photo etching method; and a fourth step for ion-implanting impurities in order to decrease the resistance of the polycrystalline silicon as contact regions to be used in resistance contacts with a fixed semiconductor region on the substrate.