Showing papers on "Strained silicon published in 1996"

Method for manufacturing a semiconductor acceleration sensor device

Abstract: On a silicon wafer there is formed a movable gate MOS transistor (sensing element: functional element). A bonding frame consisting of a silicon thin film is patterned around an element formation region on the surface of the silicon wafer. On a cap forming silicon wafer there is projectively provided a leg portion on the bottom surface of which a bonding layer consisting of a gold film is formed. The cap forming silicon wafer is disposed on the silicon wafer, whereupon heating with respect thereto is performed at a temperature equal to higher than a gold/silicon eutectic temperature to thereby make bondage between the bonding frame of the silicon wafer and the bonding layer of the cap forming silicon wafer. Thereafter, the both wafers are diced in chip units.

Production of substrate for tensilely strained semiconductor

Abstract: A process and method for producing strained and defect free semiconductor layers. In a preferred embodiment, silicon on insulator may be used as a substrate for the growth of fully relaxed SiGe buffer layers. A new strain relief mechanism operates, whereby the SiGe layer relaxes without the generation of threading dislocations within the SiGe layer. This is achieved by depositing SiGe on an SOI substrate with a superficial silicon thickness. Initially the strain in the SiGe layer becomes equalized with the thin Si layer by creating tensile strain in the Si layer. Then the strain created in the thin Si layer is relaxed by plastic deformation during an anneal. Since dislocations are formed, and glide in the thin Si layer, threading dislocations are not introduced into the upper SiGe material. A strained silicon layer for heterostructures may then be formed on the SiGe material.

Method of making self-aligned halo process for reducing junction capacitance

Abstract: A method for forming an LDD structure using a self-aligned halo process is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A gate electrode is formed overlying the gate silicon oxide layer. A silicon oxide layer is grown on the sidewalls of the gate electrode and silicon nitride spacers are formed on the sidewalls of the silicon oxide layer. First ions are implanted into the semiconductor substrate and the substrate is annealed whereby heavily doped source and drain regions are formed within the semiconductor substrate not covered by the gate electrode and the silicon oxide and silicon nitride spacers. An oxide layer is grown over the heavily doped source and drain regions. Thereafter, the silicon nitride spacers are removed. Second ions are implanted to form lightly doped regions in the semiconductor substrate not covered by the oxide layer. Third ions are implanted to form a halo having opposite dosage and a deeper junction than the lightly doped regions. An insulating layer is deposited over the surface of the substrate. An opening is provided through the insulating layer to one of the source and drain regions. A conducting layer is deposited overlying the insulating layer and within the opening and patterned completing the fabrication of the integrated circuit device.

Micromachined capillary electrophoresis device

Abstract: A micromachined structure for handling fluids with an applied high voltage, i.e. for electrophoresis, includes a glass or other highly insulative substrate on which are formed very small diameter capillary channels of e.g. silicon nitride. Due to the absence of a silicon substrate, this structure is highly electrically insulative. The silicon nitride channels are formed by a micro-machining and etch process, so that they are initially defined in an etched sacrificial silicon wafer by conformal coating of etched features in the silicon wafer with a silicon nitride layer, which is then patterned to define the desired channels. The silicon wafer is bonded to the glass substrate and the bulk of the silicon wafer is sacrificially etched away, leaving the desired silicon nitride channels with supporting silicon mesas. The remaining silicon nitride "shell" is bonded to the glass substrate and substantially duplicates the etched features in the original silicon wafer. The capillary channels are of a material such as low stress silicon nitride and there is no electrical shorting path to the highly insulative glass substrate.

Silicon on insulator (SOI) dram cell structure and process

Abstract: A silicon on insulator (SOI) DRAM has a layer of buried oxide covered by a thin layer of crystalline silicon on the surface of a bulk silicon substrate Field oxide regions are formed extending through the thin crystalline silicon surface layer and into contact with the buried oxide layer Gate oxide layers, gate electrodes and source/drain regions for the transfer FETs of the DRAM are formed in and on the thin crystalline silicon surface layer in the active regions between the field oxide regions A trench is opened through one of the source/drain regions of each of the transfer FETs A layer of doped polysilicon is provided to line the trenches and is patterned to form at least a part of the bottom electrodes of the charge storage capacitors for the DRAM The bottom electrodes are covered with a thin dielectric layer and an upper electrode of doped polysilicon is provided Preferably, the trench for the bottom capacitor electrode extends through the buried oxide layer and may extend into the bulk silicon

MOS device structure and integration method

Abstract: This invention describes a new method for forming self-aligned silicide for application in MOSFET, and a new structure of MOSFET device featuring elevated source and drain, with the objectives of reducing silicide penetration into the source and drain junctions, of eliminating junction spikes, of obtaining smoother interface between the silicide and the silicon substrate, and of reducing the chance of bridging of the silicides on the gate and on the source and drain. The new structure is made by depositing an amorphous layer of silicon on a silicon substrate already patterned with field oxide, gate oxide, polysilicon gate, and silicon nitride spacer on the gate sidewalls. Novel oxide sidewall spacers are then created by first implanting nitrogen into the horizontal surface of the amorphous silicon layer and subsequently thermally oxidizing the part of the amorphous silicon on the vertical sidewalls that is not exposed to nitrogen implantation. A dopant implantation followed by an annealing at 600° C. in nitrogen converts the deposited silicon layer into elevated source and drains. A refractory metal, such as titanium is then deposited over the substrate and, upon rapid thermal annealing, reacts with the elevated source and drain polysilicon to form silicide without consuming the substrate silicon, and without ill effect on the source/drain junctions in the single crystalline silicon. The chance of silicide bridging is greatly reduced due to the special geometry of the novel sidewall oxide spacers.

Method for depositing doped amorphous or polycrystalline silicon on a substrate

Abstract: A method for forming an in-situ doped amorphous or polycrystalline silicon thin film on a substrate is provided. The method includes placing the substrate in a reaction chamber of a CVD reactor and introducing a silicon gas species into the reaction chamber. The flow of the silicon gas species is continued for a time period sufficient to dehydrate the substrate and form a thin layer of silicon. Following formation of the thin layer of silicon, a dopant gas species is introduced into the reaction chamber and continued with the flow of the silicon gas species to form the doped silicon thin film. In an illustrative embodiment a phosphorus doped amorphous silicon thin film for a cell plate of a semiconductor capacitor is formed in a LPCVD reactor.

Process for improving roughness of conductive layer

Abstract: Disclosed is a method of fabricating hemispherical grained (HSG) silicon layers. A surface seeding method is disclosed, wherein an amorphous silicon layer is doped with germanium. The silicon may be doped with germanium during deposition, or a previously formed silicon layer may be implanted with the germanium. The layer may also be in situ conductively doped. The Ge-doped amorphous silicon is then subjected to a vacuum anneal in which surface migration of silicon atoms causes a redistribution in the layer, and hemispherical grains or bumps result. A seeding source gas may flow during the anneal to aid in nucleation. The method permits HSG silicon formation at lower temperature and shorter duration anneals than prior art methods. Greater silicon mobility in the presence of germanium dopants also enables the growth of larger grains, thus enhancing surface area. At the same time, the germanium provides conductivity for memory cell charge storage.

Epitaxial oxides on amorphous SiO2 on single crystal silicon

Abstract: A process for forming a structure including an epitaxial layer of a oxide material such as yttria-stabilized zirconia on a thick layer of amorphous silicon dioxide having a thickness of at least about 500 Angstroms on a single crystal silicon substrate and the resultant structures derived therefrom are provided.

Method of doping crystalline silicon film

Abstract: After an ion having n-type or p-type impurity necessary for a crystalline silicon film is implanted by a known ion implantation or ion doping, a laser light or an equivalent intense light is irradiated onto the crystalline silicon film, to thereby improve the crystallinity of the silicon film and activate the impurity, and in the succeeding process, the silicon film is not thermally annealed at 450° C. or higher. Also, under a state where a substrate is heated at 50 to 500° C., preferably 200 to 350° C., an ion having n-type or p-type impurity necessary for a crystalline silicon film is implanted by the ion doping, and in the succeeding process, the silicon film is not thermally annealed at 450° C. or higher.

Deep trench filling method using silicon film deposition and silicon migration

Abstract: A method of filling one or more trenches formed in a silicon substrate includes the steps of forming a thin polycrystalline silicon film in a trench such that the thin polycrystalline silicon film is sufficiently thin so as to not close the trench; forming an amorphous silicon film on thin polycrystalline film and the surface of the substrate and in the trenches; and annealing the amorphous silicon film such that the amorphous silicon layer migrates to fill the trenches to a first level. The deposition and annealing steps are performed in ambient atmospheres having low partial pressures of H 2 O and O 2 , the annealing temperature is higher than the deposition temperature, and the annealing pressure is greater than the deposition pressure.

Method of manufacturing a raised source/drain MOSFET

Abstract: A method of manufacturing a raised source/drain MOSFET by depositing amorphous silicon on the partially formed MOSFET having the gate and gate oxide spacers formed, ion implanting to form the appropriate source/drain junctions, annealing wherein epitaxial growth takes place in regions where the amorphous silicon is over silicon, and etching the remaining amorphous silicon. A layer of refractory metal is deposited and a second anneal converts the refractory metal overlaying silicon to silicide.

Using neutral metastable argon atoms and contamination lithography to form nanostructures in silicon, silicon dioxide, and gold

Abstract: This letter describes the fabrication of ∼80 nm structures in silicon, silicon dioxide, and gold substrates by exposing the substrates to a beam of metastable argon atoms in the presence of dilute vapors of trimethylpentaphenyltrisiloxane, the dominant constituent of diffusion pump oil used in these experiments. The atoms release their internal energy upon contacting the siloxanes physisorbed on the surface of the substrate, and this release causes the formation of a carbon‐based resist. The atomic beam was patterned by a silicon nitride membrane, and the pattern formed in the resist material was transferred to the substrates by chemical etching. Simultaneous exposure of large areas (44 cm2) was also demonstrated.

Investigation of charge carrier injection in silicon nitride/silicon junctions

Abstract: Contactless measurements of the conductance of silicon wafers with silicon nitride top layers are presented. The deposition of silicon nitride layers leads to an increase of the conductance, both for p‐Si and n‐Si. This is attributed to the increase of the number of electrons in the Si wafer, in an inversion layer in p‐Si, and in an accumulation layer in n‐Si. Comparison of the increase of the conductance with the fixed charge density in the nitride layer points to a strongly reduced electron mobility in these layers. It is shown that the change of the conductance increases with growing thickness of the nitride layer up to a thickness of 20 nm, whereafter a constant value is attained.

Fabrication method for a semiconductor device

Abstract: A semiconductor device and a fabrication method thereof are disclosed. A silicon nitride film is formed over a silicon semiconductor substrate. Impurity ions are then implanted into desired areas of the silicon semiconductor substrate, so that nitrogen atoms and silicon atoms from the silicon nitride film are incorporated into the surface of the silicon semiconductor substrate together with introduction of impurity ions. The silicon semiconductor substrate has a minimized content of oxygen mixed thereinto and restored crystal defects filled by nitrogen atoms upon implanting of impurity ions. The fabricated semiconductor device is free from a trade-off relation between gate-electrode depletion and junction current leakage, and short-channel effects.

Semiconductor device having a silicon-on-insulator structure

Abstract: A semiconductor device of SOI structure exhibits a excellent heat-radiating characteristic while assuring breakdown-voltage and element-isolating performance. A buried silicon oxide film having a thickness required by the breakdown-voltage of a semiconductor element is buried between a SOI layer and a silicon substrate. A SOI layer is divided into island silicon regions by a groove for electrical-isolation use, and the groove is filled with dielectric such as an oxide film and polycrystalline silicon. In an island silicon region, a LDMOS transistor having high breakdown voltage may be formed as the semiconductor element, and potential distribution is created in accordance with a voltage application to the semiconductor element. The buried silicon oxide film at a region where low electric potential is distributed, for example a region below a grounded well region of the LDMOS transistor, is made thin. Through the thin portion of the buried silicon oxide film, heat generated by the operation of the semiconductor element can easily be propagated to the silicon substrate and radiated.

Calculation of the fractional interstitial component of boron diffusion and segregation coefficient of boron in Si0.8Ge0.2

Abstract: Investigation of boron diffusion in strained silicon germanium buried layers reveals a fractional interstitial component of boron diffusion (fBI) in Se0.8Ge0.2 approximately equal to the fBI value in silicon. In conjunction with computer‐simulated boron profiles, the results yield an absolute lower‐bound of fBI in Si0.8Ge0.2 of ∼0.8. In addition, the experimental methodology provides a unique vehicle for measuring the segregation coefficient; oxidation‐enhanced diffusion is used instead of an extended, inert anneal to rapidly diffuse the dopant to equilibrium levels across the interface, allowing the segregation coefficient to be measured more quickly.

Below threshold conduction in a‐Si:H thin film transistors with and without a silicon nitride passivating layer

Abstract: We report temperature measurements of inverted staggered amorphous silicon thin film transistor subthreshold conductance for devices with and without a top silicon nitride passivating layer. Subthreshold conductance activation energies clearly show the different conductance paths in the active layer of these devices. Transistors with no top nitride layer conduct in the bulk amorphous silicon, whereas the devices with a top nitride layer conduct at the interface between the amorphous silicon and the top nitride (a ‘‘back’’ channel). Gate bias stressing and light soaking experiments uphold the existence of the back channel. We also present two‐dimensional simulations that support our interpretation of the experimental data.

Coulomb scattering in strained‐silicon inversion layers on Si1−xGex substrates

Abstract: Results of electron mobility in strained‐Si inversion layers grown on Si1−xGex substrates are reported Drift velocities are calculated by Monte Carlo simulations including electron quantization and Coulomb scattering, in addition to phonon and surface roughness scattering The strain is shown to contribute as well to the enhancement of the Coulomb‐limited mobility due to better screening of the interface centers by the mobile carriers Even in the case of high‐doped substrates, Coulomb scattering does not cancel the mobility enhancement provided by the reduction of both intervalley scattering and conduction effective mass

Methods of forming silicon carbide semiconductor devices having buried silicon carbide conduction barrier layers therein

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, an active layer in the substrate and a silicon carbide buried layer which provides a conduction barrier between the substrate and at least a portion of the active layer. The buried layer is preferably formed by implanting second conductivity type dopants into the substrate so that a P-N junction barrier is provided between the active layer and the substrate. The buried layer may also be formed by implanting electrically inactive ions into the substrate so that a relatively high resistance barrier is provided between the active layer and the substrate. The electrically inactive ions are preferably selected from the group consisting of argon, neon, carbon and silicon, although other ions which are electrically inactive in silicon carbide may be used. The implantation of the electrically inactive ions is designed to cause the formation of a large number of electrically active deep level defects in the buried layer, particularly near the peak of the implant profile which is Gaussian in shape. These steps can be utilized in the formation of a variety of silicon carbide semiconductor devices such as lateral field effect devices and devices having both vertical and lateral active regions which are designed for high power applications. In particular, lateral silicon carbide-on-insulator enhancement and depletion mode field effect transistors (FETs) can be formed in accordance with the present invention. Vertical silicon carbide power MESFET devices can also be formed by incorporating a silicon carbide source region in the active layer at the first face of a silicon carbide substrate and a drain region at the second face and by providing a Schottky barrier gate electrode on the first face.

Method of making a polysilicon carbon source/drain heterojunction thin-film transistor

Abstract: The present invention includes forming a conductive layer on a substrate. Portions of the conductive layer are removed using a first photoresist layer as a mask. A first oxide layer is formed over the conductive layer and the substrate, and an amorphous silicon layer is then formed on the first oxide layer. After annealing the amorphous silicon layer, thereby transforming amorphous silicon layer to a polysilicon layer, a second oxide layer is formed on the polysilicon layer. The second oxide layer is removed using a second photoresist layer as a mask. An amorphous silicon carbon layer is formed over the second oxide layer and the polysilicon layer, and a heavily-doped amorphous silicon carbon layer is formed on the amorphous silicon carbon layer. After annealing the heavily-doped amorphous silicon carbon layer and the amorphous silicon carbon layer, thereby transforming the heavily-doped amorphous silicon carbon layer to a heavily-doped polysilicon carbon layer, and transforming the amorphous silicon carbon layer to a polysilicon carbon layer, portions of the polysilicon carbon layer, the heavily-doped polysilicon carbon layer and the polysilicon layer are removed using a third photoresist layer as a mask.

Carrier transport in amorphous silicon-based thin-film transistors studied by spin-dependent transport

Abstract: Carrier transport processes in hydrogenated amorphous silicon-based thin-film transistors (a-Si:H TFT's) are investigated by spin-dependent transport (SDT). Spin-dependent photoconductivity (SDPC) signals arising from less than ${10}^{6}$ spins in a small transistor are detected with an adequate signal-to-noise ratio. SDPC measurements reveal two different limiting steps for the light-induced leakage current in TFT's depending on the gate voltage: bulk recombination in undoped a-Si:H and recombination near the source junction. Also, the leakage current mechanism under high source-drain fields is identified by SDT measurements in the dark as electron hopping via defect states located at the interface between undoped a-Si:H and the passivation silicon nitride layer. Both silicon dangling bonds and nitrogen dangling bonds seem to be involved in the electron hopping process. At temperatures below 100 K, spin-dependent hopping of electrons in conduction-band tail states is observed. The change of the dominant transport path from extended state conduction to variable range hopping conduction with decreasing temperature is confirmed by SDT measurements. \textcopyright{} 1996 The American Physical Society.

Accelerometers using silicon on insulator technology

Abstract: Process for the production of accelerometers using the silicon on insulator method. The process comprises the following stages: a) producing a conductive monocrystalline silicon film on a silicon substrate and separated from the latter by an insulating layer; b) etching the silicon film and the insulating layer up to the substrate in order to fix the shape of the mobile elements and the measuring device; c) producing electric contacts for the measuring devices; d) partial elimination of the insulating layer in order to free the mobile elements, the remainder of the insulating layer rendering integral the substrate and the moving elements.

Ultra shallow junction formation using amorphous silicon layer

Abstract: A method of achieving shallow junctions in a semiconductor device is achieved by providing an amorphous silicon layer over an epitaxial layer, implanting ions into the amorphous silicon layer, and annealing the resulting device to recrystallize the amorphous silicon layer and drive in the implanted ions to a shallow depth less than the depth of the amorphous silicon layer.

Low-temperature dopant activation and its application to polycrystalline silicon thin film transistors

Abstract: Low‐temperature activation of dopants in amorphous silicon films was achieved by a new method and high‐performance polycrystalline silicon thin film transistors were fabricated through its application. It was found that the dopants implanted into amorphous silicon were activated simultaneously with the crystallization of amorphous silicon. With the help of a thin nickel layer, the thermal budget for dopant activation and crystallization was considerably reduced, from 600 °C (30 h) to 500 °C (5 h). Even without plasma hydrogenation, the n‐channel polycrystalline silicon thin film transistors fabricated at temperatures below 500 °C showed a mobility of 120 cm2/V s, which is much higher than that of conventional devices fabricated at 600 °C.

Method of forming a silicon film

Abstract: A method of forming a silicon layer having a roughened outer surface includes, a) providing a substantially amorphous silicon layer over a substrate, the amorphous silicon layer having an outer surface; b) providing a seeding layer over the amorphous silicon layer outer surface; and c) annealing the amorphous silicon layer and seeding layer under temperature and pressure conditions effective to transform said amorphous layer into a silicon layer having a roughened outer surface. The amorphous silicon layer is preferably provided by providing a first silicon source gas (i.e., silane) within a chemical vapor deposition reactor under first reactive temperature and pressure conditions effective to deposit a substantially amorphous first silicon layer on the substrate. After the amorphous silicon layer deposition, a second silicon source gas (i.e., silane) is provided within the chemical vapor deposition reactor under second reactive temperature and pressure conditions effective to deposit a seeding second layer of polysilicon on the amorphous first silicon layer, the second reactive conditions also being effective to maintain the first silicon layer substantially amorphous during the second silicon layer deposition. Then, the first and second silicon layers are annealed under temperature and pressure conditions effective to transform said amorphous first layer into a silicon layer having a roughened outer surface.

Method for producing a thin film transistor

Abstract: In producing a semiconductor device such as a thin film transistor (TFT), a silicon semiconductor film is formed on a substrate having an insulating surface, such as a glass substrate, and then a silicon nitride film is formed on the silicon semiconductor film. After that, a hydrogen ion, fluorine ion, or chlorine ion is introduced into the silicon semiconductor film through the silicon nitride film, and then the silicon semiconductor film into which an ion is introduced is heated in an atmosphere containing hydrogen, fluorine, chlorine or these mixture, to neutralize dangling bonds in the silicon semiconductor film and reduce levels in the silicon semiconductor film.