Showing papers on "Stuck-at fault published in 1996"

Design of unknown input observers and robust fault detection filters

Abstract: Fault detection filters are a special class of observers that can generate directional residuals for the purpose of fault isolation. This paper proposes a new approach to design robust (in the disturbance de-coupling sense) fault detection filters which ensure that the residual vector, generated by this filter, has both robust and directional properties. This is done by combining the unknown input observer and fault detection filter principles. The paper proposes a new full-order unknown input observer, and gives necessary and sufficient conditions for its existence. After the disturbance de-coupling conditions are satisfied, the remaining design freedom can be used to make the residual have the directional property, based on the fault detection filter principle. A nonlinear jet engine system is used to illustrate the robust fault isolation approach presented. It is shown that linearization errors can be approximately treated as unknown disturbances and be de-coupled in the design of a robust fault detect...

HOPE: an efficient parallel fault simulator for synchronous sequential circuits

Abstract: HOPE is an efficient parallel fault simulator for synchronous sequential circuits that employs the parallel version of the single fault propagation technique. HOPE is based on an earlier fault simulator railed PROOFS, which employs several heuristics to efficiently drop faults and to avoid simulation of many inactive faults. In this paper, we propose three new techniques that substantially speed up parallel fault simulation: (1) reduction of faults simulated in parallel through mapping nonstem faults to stem faults, (2) a new fault injection method called functional fault injection, and (3) a combination of a static fault ordering method and a dynamic fault ordering method. Based on our experiments, our fault simulator, HOPE, which incorporates the proposed techniques, is about 1.6 times faster than PROOFS for 16 benchmark circuits.

A new approach to on-line turn fault detection in AC motors

Abstract: Turn fault detection is based on the principal that symmetrical (unfaulted) motors powered by symmetrical multiphase voltage sources will have no negative sequence currents flowing in the leads. A turn-to-turn fault will break that symmetry and give rise to a negative sequence current which may then be used as a measure of fault severity or to initiate protective action such as a circuit breaker trip. A new way of looking at the effects of turn faults has been developed that improves sensitivity and speed while reducing the probability of misdetection, taking into account voltage balance, load or voltage variation and instrument errors. The method has been implemented on a PC and tested, in real time, on a specially prepared small motor. Reliable detection of one shorted turn out of 648 turns per phase (in a Y connected motor) was demonstrated with the fault indicator becoming fully developed in two cycles of line frequency after initiation of the fault.

Unsynchronized two-terminal fault location estimation

Abstract: A technique for power system fault location estimation which uses data from both ends of a transmission line and which does not require the data to be synchronized is described. The technique fully utilizes the advantages of digital technology and numerical relaying which are available today and can easily be applied for offline analysis. This technique allows for accurate estimation of the fault location irrespective of the fault type, fault resistance, load currents, and source impedances. Use of two-terminal data allows the algorithm to eliminate previous assumptions in fault location estimation, thus increasing the accuracy of the estimate. The described scheme does not require real-time communications, only offline post-fault analysis. The paper also presents fault analysis techniques utilizing the additional communicated information.

Network fault correlation

Abstract: A method and apparatus for correlating faults in a networking system. A database of fault rules is maintained along with and associated probable causes, and possible solutions for determining the occurrence of faults defined by the fault rules. The fault rules include a fault identifier, an occurrence threshold specifying a minimum number of occurrences of fault events in the networking system in order to identify the fault, and a time threshold in which the occurrences of the fault events must occur in order to correlate the fault. Occurrences of fault events in the networking system are detected and correlated by determining matched fault rules which match the fault events and generating a fault report upon determining that a number of occurrences for the matched fault rules within the time threshold is greater than or equal to the occurrence threshold for the matched fault rules.

System and method for performing real time data acquisition, process modeling and fault detection of wafer fabrication processes

Abstract: A system and method for detecting faults in wafer fabrication process tools by acquiring real-time process parameter signal data samples used to model the process performed by the process tool. The system includes a computer system including a DAQ device, which acquires the data samples, and a fault detector program which employs a process model program to analyze the data samples for the purpose of detecting faults. The model uses data samples in a reference database acquired from previous known good runs of the process tool. The fault detector notifies a process tool operator of any faults which occur thus potentially avoiding wafer scrap and potentially improving mean time between failures. The fault detector also receives notification of the occurrence of process events from the process tool, such as the start or end of processing a wafer, which the fault detector uses to start and stop the data acquisition, respectively. The fault detector also receives notification of the occurrence of a new process recipe and uses the recipe information to select the appropriate model for modeling the data samples. The fault detector employs a standard data exchange interface, such as DDE, between the fault detector and the model, thus facilitating modular selection of models best suited to the particular fabrication process being modeled. Embodiments are contemplated which use a UPM model, a PCA model, or a neural network model.

Constructive multi-phase test point insertion for scan-based BIST

Abstract: This paper presents a novel test point insertion technique which, unlike the previous ones, is based on a constructive methodology. A divide and conquer approach is used to partition the entire test into multiple phases. In each phase a group of test points targeting a specific set of faults is selected. Control points within a particular phase are enabled by fixed values, resulting in a simple and natural sharing of the logic driving them. Experimental results demonstrate that complete or near-complete stuck-at fault coverage can be achieved by the proposed technique with the insertion of a few test points and a minimum number of phases.

A fault injection technique for VHDL behavioral-level models

Abstract: Designers are realizing the advantages of performing fault injection early, using simulation to inject faults into a model of the design rather than the actual system. The authors describe their technique for injecting faults into a system's VHDL behavioral level model. To demonstrate the technique, they evaluate an embedded control system providing fail safe operation in the railway industry.

A gate-level simulation environment for alpha-particle-induced transient faults

Abstract: Mixed analog and digital mode simulators have been available for accurate /spl alpha/-particle-induced transient fault simulation. However, they are not fast enough to simulate a large number of transient faults on a relatively large circuit in a reasonable amount of time. In this paper, we describe a gate-level transient fault simulation environment which has been developed based on realistic fault models. Although the environment was developed for /spl alpha/-particle-induced transient faults, the methodology can be used for any transient fault which can be modeled as a transient pulse of some width. The simulation environment uses a gate level timing fault simulator as well as a zero-delay parallel fault simulator. The timing fault simulator uses logic level models of the actual transient fault phenomenon and latch operation to accurately propagate the fault effects to the latch outputs, after which point the zero-delay parallel fault simulator is used to speed up the simulation without any loss in accuracy. The environment is demonstrated on a set of ISCAS-89 sequential benchmark circuits.

Segment delay faults: a new fault model

Abstract: We propose a segment delay fault model to represent any general delay defect ranging from a spot defect to a distributed defect. The segment length, L, is a parameter that can be chosen based on available statistics about the types of manufacturing defects. Once L is chosen, the fault list contains all segments of length L and paths whose entire lengths are less than L. Both rising and falling transitions at the origin of segments are considered. Choosing segments of a small length can prevent an explosion of the number of faults considered. At the same time, a defect over a segment may be large enough to affect any path passing through it. We present an efficient algorithm to compute the number of segments of any possible length in a circuit. We define various classes of segment delay fault tests-robust, transition, and non-robust-that offer a trade-off between fault coverage and quality.

An approach for testing programmable/configurable field programmable gate arrays

Abstract: This paper presents a new general technique for testing field programmable gate arrays (FPGAs) by fully exploiting their programmable and configurable characteristics. A hybrid fault model is introduced based on a physical and behavioral characterization; this permits the detection of a single fault, as either a stuck-at or a functional fault. A general approach which regards testing as can application for the reconfigurable FPGA, is then proposed. It is shown that different arrangements of disjoint one-dimensional arrays with unilateral horizontal connections and common vertical input lines provide a very good solution. A further feature that is considered for array testing, is the relation between the configuration of the logic blocks and the number of I/O pins in the chip. As an example, the proposed approach is applied for testing the Xilinz 4000 family of FPGAs.

Fault tree analysis and binary decision diagrams

Abstract: Fault tree analysis is now commonly used to assess the adequacy, in reliability terms, of industrial systems. For complex systems, an analysis may produce thousands of combinations of events which can cause system failure (minimal cut sets). The determination of these minimal cut sets can be a very time consuming process even on modern high speed digital computers. Also, if the fault tree has many minimal cut sets, calculating the exact top event probability will require extensive calculations. For many complex fault trees this requirement is beyond the capability of the available machines, thus approximation techniques need to be introduced resulting in loss of accuracy. This paper describes the use of a binary decision diagram for fault tree analysis and some ways in which it can be efficiently implemented on a computer. The work to date shows a substantial improvement in computational effort for large, complex fault trees analysed with this method in comparison to the traditional approach. The binary decision diagram method has the additional advantage that as approximations are not required, exact calculations for the top event parameters can be performed.

Beyond the byzantine generals: unexpected behavior and bridging fault diagnosis

Abstract: Physical defects cause behaviors unmodeled by even the best fault simulators, which complicates predictive diagnosis. This paper reports on a diagnosis procedure that uses modified composite signatures constructed from single stuck-at information combined with a lexicographic matching and ranking algorithm. The diagnosis procedure is used to perform high-quality bridging fault diagnosis for more than 400,000 diagnostic experiments involving dropping or adding behaviors from the simulations of faulty circuits.

Analog testing with time response parameters

Abstract: This paper describes a simple test generation technique which derives sinusoidal test waveforms that detect several fault classes In addition, the authors show that certain stimuli will provoke variations in delay, rise time, and overshoot that indicate faulty behavior Simple algorithms compute the different parameters

Fault location on two-terminal transmission lines based on voltages

Abstract: A new method for locating faults in two-terminal transmission lines is discussed. The procedure is based on the fundamental components of fault and prefault voltage at 50/60 Hz measured at the two ends of a transmission line. The methodology allows one to establish a direct calculation procedure that is independent of fault and prefault currents, fault type, fault resistance, synchronisation condition of register devices located on line ends, and prefault condition, either balanced or not. This is achieved by defining a new concept called ‘distance factor’. The technique developed was validated at two levels: first, from exact data obtained using a fault simulation software program, which allows the accuracy to be evaluated, and secondly, from erroneous voltage data taken at the ends of the line or from erroneous source impedances, which allows assessment of the sensitivity against incorrect data.

Principles of fault tolerance

Abstract: The demand for continuously available electronic systems increases every day. Transaction processing, communications systems, and critical processes all require nonstop, fault tolerant operation. Creating a fault tolerant or highly available system can be achieved by following four basic principles: redundancy, fault isolation, fault detection and annunciation, and on-line repair. This paper is a tutorial that presents those four principles after reviewing some fundamentals of reliability and availability. It concludes with an expanded discussion on implementing redundancy. Special considerations for high availability and fault tolerance in distributed power systems are highlighted.

Fault observability analysis of analog circuits in frequency domain

Abstract: We study the testability of analog circuits in the frequency domain by introducing the analog fault observability concept. The proposed algorithm indicates the set of adequate test frequencies and test nodes to increase fault observability. This approach combines a structural testing methodology with functionality verification to increase the test effectiveness and consequently the design manufacturability and reliability. We analyze the case of single fault, double, and multiple faults. Concepts such as fault masking, fault dominance, fault equivalence, and non observable fault in analog circuits are defined and then used to evaluate testability. The theoretical aspect is based on the sensitivity approach.

An FPGA-based hardware emulator for fast fault emulation

Abstract: An FPGA-based hardware emulation system is shown to boost the speed of fault simulation for sequential circuits. The circuit is downloaded into the emulation system which emulates the faulty circuit's behavior by synthesizing from the good circuit and the given fault list in a novel way. Fault injection is made easy by shifting the content of a fault injection chain, with which we get rid of the highly time-consuming bit-stream regeneration process. Experimental results for ISCAS-89 benchmark circuits show that the fault emulator is about twenty times faster than HOPE (parallel fault simulator). A parallel fault emulation approach is also proposed, in which faults that are not activated or with short propagation distance are screened off before fault emulation, and non-stem faults are collapsed into their equivalent stem faults, further reducing the number of faults actually emulated.

Method and circuit for protecting power circuits against short circuit and over current faults

Abstract: A fault protection circuit for protecting IGBT's and other non-latching semiconductor devices in power circuits, for example, power converting/inverting circuits, against phase to phase, phase to earth and shoot through short circuit faults as well as against over current faults. The circuit provides local protection for devices on the high side of such power circuits, and transfers the fault to the low side where it is detected and appropriate control circuitry is activated to latch the fault, thereby avoiding the need for isolcated sensing or feedback to protect the high side devices as well as the complete power circuit.

Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets

Abstract: An automatic test pattern generation (ATPG) procedure for linear analog circuits is presented in this work. A fault-based multifrequency test approach is considered. The procedure selects a minimal set of test measures and generates the minimal set of frequency tests which guarantee maximum fault coverage and, if required, maximal fault diagnosis, of circuit AC hard/soft faults. The procedure is most suitable for linear time-invariant circuits which present significant frequency-dependent fault effects. For test generation, the approach is applicable once parametric tests have determined DC behaviour. The advantage of this procedure with respect to previous works is that it guarantees a minimal size test set. For fault diagnosis, a fault dictionary containing a signature of the effects of each fault in the frequency domain is used. Fault location and fault identification can be achieved without the need of analog test points, and just in-circuit checkers with an observable go/no-go digital output are required for diagnosis. The procedure is exemplified for the case of an analog biquadratic filter. Three different self-test approaches for this circuit are considered. For each self-test strategy, a set of several test measures is possible. The procedure selects, in each case, the minimal set of test measures and the minimal set of frequency tests which guarantee maximum fault coverage and maximal diagnosis. With this, the self-test approaches are compared in terms of the fault coverage and the fault diagnosability achieved.

On-line fault detection and diagnosis obtained by implementing neural algorithms on a digital signal processor

Abstract: A measurement instrument for on-line fault detection and diagnosis is proposed. It is based on the implementation of a neural network algorithm on a processor specialized in digital signal processing and provided with suitable data acquisition and generation units. Two specific implementations are detailed. The former uses the neural-network to simulate on-line the correct system behavior, thus allowing the fault detection to be achieved by comparing the neural network output with the measured one. The latter uses the neural network to classify on-line the system as correct or faulty, thus allowing the fault detection and diagnosis to be achieved simultaneously. These two implementations are applied to detect on-line and diagnose faults on a real system in order to point out different fields of application and to highlight the performance of the measurement apparatus.

Automatic test generation using genetically-engineered distinguishing sequences

Abstract: A fault-oriented sequential circuit test generator is described in which various types of distinguishing sequences are derived, both statically and dynamically, to aid the test generation process. A two-phase algorithm is used during test generation. The first phase activates the target fault, and the second phase propagates the fault effects (FE's) from the flip-flops with assistance from the distinguishing sequences. This strategy improves the propagation of FE's to the primary outputs, and the overall fault coverage is greatly increased. In our new test generator, DIGATE, genetic algorithms are used to derive both activating and distinguishing sequences during test generation. Our results show very high fault coverages for the ISCAS89 sequential benchmark circuits and several synthesized circuits.

Method and apparatus for diagnosing fault states in a computer system

Abstract: Faults in a computer system having circuits are managed by fault detectors connected to detect fault states of respective circuits. A fault manager associates the fault states with the respective circuits. The fault manager includes a system manager connected to identify which of the circuits is causing faulty operation in the computer system. The fault detectors associated with the respective circuits are configured to detect faulty operation of and to generate fault state information for the respective circuits. A central manager is connected to accumulate fault state information from the fault detectors. One of the circuits includes a bus, and the fault state includes a bus error condition. The bus is connected to multiple devices, and the fault manager identifies which of the multiple devices causes the bus error condition. One of the circuits includes multiple modules, and the fault manager identifies fault states of the multiple modules. The modules include state machines. One of the circuits includes an internal clock, and the fault state of the circuit includes the internal clock not functioning properly. One of the circuits includes a temperature sensor, and the fault state of the circuit includes a high temperature condition detected by the temperature sensor.

Fault tree models for the analysis of complex computer-based systems

Abstract: In this paper we present a synthesis of several techniques into a single methodology that can solve both dynamic and static fault trees, and which is applicable to the analysis of hardware, software and humanware in complex computer-based systems. The methodology combines those techniques into a unified fault tree methodology which we call SHADE Tree. SHADE Tree provides a high-level decomposition of the system fault tree model into the static and dynamic fault trees. Static fault trees, which contain only traditional fault tree gates (i.e. AND, OR, R-of-N, etc.) are solved using the binary decision diagram approach. Dynamic fault trees, which contain at least one special dynamic gate as well as traditional fault tree gates, are solved using Markov methods.

Neural network approach to fault detection in electric power systems

Abstract: This paper describes a fault detector that uses artificial neural networks (ANN). It represents the first step to the development of a neural distance relay for protecting transmission lines. We envisage the fault detection problem as a pattern classification process. Our suggested approach is based on the fact that when a fault occurs, a change in the system impedance takes place and, as a consequence, the current phase and amplitude change. The ANN-based fault detector is trained to detect this changes as indicators of the instant of fault inception. Results showing the performance of the fault detector are presented in the paper, indicating that it is fast, robust and accurate.

Advanced techniques for GA-based sequential ATPGs

Abstract: Genetic Algorithms (GAs) have been recently investigated as an efficient approach to test generation for synchronous sequential circuits. In this paper we propose a set of techniques which significantly improves the performance of the GA-based ATPG algorithm proposed by Prinetto et al. (1994): in particular, the new techniques enhance the capability of the algorithm in terms of test length minimization and fault excitation. We report some experimental results gathered with a prototypical tool and show that a well-tuned GA-based ATPG is generally superior to both symbolic and topological ones in terms of achieved fault coverage and required CPU time.

On the effects of test compaction on defect coverage

Abstract: We study the effects of test compaction on the defect coverage of test sets for modeled faults. Using a framework proposed earlier, defects are represented by surrogate faults. Within this framework, we show that the defect coverage does not have to be sacrificed by test compaction, if the test set is computed using appropriate test generation objectives. Moreover, two test sets, one compacted and one non-compacted, generated using the same test generation objectives, typically have similar defect coverages, even if the compacted one is significantly smaller than the uncompacted one. Test generation procedures and experimental results to support these claims are presented.

Defect-oriented vs schematic-level based fault simulation for mixed-signal ICs

Abstract: Escalating demand for mixed-signal Integrated Circuits has been accompanied by the need to develop efficient strategies to guarantee higher quality at lower cost. One key to achieving this is efficient production test and the utilization of Design-for-Testability (DfT). Fault simulation based test evaluation would be a major contribution towards measuring and optimizing the effectiveness of a production test. Fault simulations, however, are only useful if the underlying fault list generation approaches accurately reflect manufacturing defects-both in their probability of occurrence and in their electrical behavior. This paper evaluates and compares two fault list generation approaches and the implications on test optimization. Fault lists derived from both Inductive Fault Analysis (IFA) and a transistor fault-model are compared for a testability analysis on a self-test function for a high-performance switched-current design.