Showing papers on "Subthreshold conduction published in 1987"

The impact of gate-induced drain leakage current on MOSFET scaling

Abstract: Significant gate-induced drain leakage current can be detected in thin gate oxide MOSFETs at drain voltages much lower than the junction breakdown voltage. This current is found to be due to the band-to-band tunneling occurring in the deep-depletion layer in the gate-to-drain overlap region. In order to limit the leakage current to 0.1pA/µm, the oxide field in the gate-to-drain overlap region must be limited to 1.9MV/cm. This may set another constraint for the power supply voltage and/or oxide thickness in VLSI MOSFET scaling Device design considerations for minimizing the gate-induced drain leakage current are discussed.

Modeling of transconductance degradation and extraction of threshold voltage in thin oxide MOSFET's

Abstract: In this paper, we discuss the low-drain voltage transconductance behavior of the MOSFET due to surface mobility variation, interface states and small geometry, and its application in threshold voltage determination. We modify the Pao-Sah drain current model to incorporate a mobility model and obtain 3% accuracy from subthreshold to very strong inversion for a wide range of substrate biases. The effects of non-ideal scaling, finite inversion layer thickness, surface roughness mobility degradation under high normal electric fields and interface states on the transconductance behavior are discussed. We observe the peak transconductance increases with substrate bias in short-channel devices and decreases with substrate bias in long-channel devices. Finally, we show the threshold voltage can be determined from the gate voltage at which the rate of transconductance change ( ∂g m ∂V GS ) is a maximum. This threshold voltage is identifiable with a known band-bending (surface potential) of the substrate (φ s ⋍ 2φ F + V SB ) , from which the band-bending at all gate biases can be calculated. The transconductance change (TC) method is insensitive to device degradations (e.g. mobility, series resistance, hot-carrier) in contrast to the conventional method of linear extrapolation to zero drain current.

The relationship between Oxide charge and device degradation: A comparative study of n- and p- channel MOSFET's

Abstract: We present a comparative study of device degradation for conventional n- and p-channel MOSFET's. The experimentally determined features of degradation are investigated with a 2-D simulation including fast and slow interface states as well as channel mobility degradation due to Coulomb scattering off these charges. Three different models concerning kind and spatial distribution are studied. We present a model that self-consistently describes the observed experimental features in the pentode and subthreshold regimes of the device. Furthermore, the substrate current is included in this analysis.

High‐temperature depletion‐mode metal‐oxide‐semiconductor field‐effect transistors in beta‐SiC thin films

Abstract: Depletion‐mode n‐channel metal‐oxide‐semiconductor field‐effect transistors were fabricated on n‐type β‐SiC (111) thin films epitaxially grown by chemical vapor deposition on the Si (0001) face of 6H α‐SiC single crystals. The gate oxide was thermally grown on the SiC; the source and drain were doped n+ by N+ ion implantation at 823 K. Stable saturation and low subthreshold current were achieved at drain voltages exceeding 25 V. Transconductances as high as 11.9 mS/mm were achieved. Stable transistor action was observed at temperatures as high as 923 K, the highest temperature reported to date for a transistor in any material.

Post-Irradiation Effects in Field-Oxide Isolation Structures

Abstract: We have studied experimentally the time dependence of leakage currents in six CMOS (complementary metaloxide semiconductor) processes using LOCOS (local oxidation of silicon) isolation structures. These six process lines represent six different U. S. semiconductor companies. In their radiation response, these processes range from very hard to very soft. In the softer processes, the radiation-induced leakage currents are due to the turning on of a leakage path either under the thick field-oxide or along the transistor edge (bird's beak) region. In the hardest process, the field-oxide did not turn on, and the leakage was entirely due to subthreshold current in the gate region. These different mechanisms have qualitatively different time dependences, which we describe and discuss. We also discuss the implications of our results for hardness assurance testing.

Performance and hot-carrier effects of small CRYO-CMOS devices

Abstract: The performance characteristics of submicrometer CMOS devices operating at low/cryogenic temperatures (CRYO-CMOS) are determined. The advantages and problems in a CRYO-CMOS technology are experimentally studied in relation to the velocity saturation, source-drain resistances, mobility behavior, carrier freeze-out effects, hot-carrier effects, and circuit performance. The increase of the maximum transconductance at low temperatures (77, 4.2 K) has been confirmed even in the submicrometer channel region. However, improvement of inabilities at a V G nearly equal to 5 V is not so significant in devices with thinner oxides and less so in pMOS devices than in nMOS devices. Excellent subthreshold characteristics have been obtained at low temperatures, making very low-voltage operation possible. One problem found in the threshold control of pMOS transistors is that the boron ions implanted in the surface freeze out, causing unusual subthreshold behavior. Circuit delays have been improved by a factor of 2 to 3, and CRYO-CMOS shows the lowest power-delay product among existing semiconductor technologies with speed performance comparable to bipolar ECL devices. For LDD devices, speed improvements are only slightly smaller than for single-drain devices, while currents and transconductances in the linear regions are limited because of carrier freeze-out of the lightly doped drain. For both channel LDD devices, the transconductance degradations and V T shifts observed under dc stress conditions at 77 K are considered to result from electron injection into spacer oxides.

Anomalous subthreshold current—Voltage characteristics of n-channel SOI MOSFET's

Abstract: The abnormally high slopes of the subthreshold current-voltage characteristics exhibited by n-channel silicon-on-insulator (SOI) MOSFET's are experimentally related to defect density (off-state leakage current) as well as drain voltage and channel length, and a theoretical physical description of the measured relations is presented and supported. The anomalous subthreshold behavior is attributed analytically to the (floating) body effect due to charging (biasing) by impact ionization at the drain.

Generation of Interface States by Ionizing Radiation at 80K Measured by Charge Pumping and Subthreshold Slope Techniques

Abstract: Generation of fast interface states D11 by ionizing radiation has been measured in MOS transistors at 80K and 295K using charge pumping and subthreshold slope techniques. Using charge pumping, the more sensitive and reliable technique, we find that D11 are not formed by radiation at 80K. In contrast, subthreshold slope measurements appear to show an increase in D11 in MOSFETs irradiated at 80K. This is shown to be an artifact caused by lateral non-uniformities (LNU) in the radiation-induced fixed charge.

Subthreshold model of a polycrystalline silicon thin‐film field‐effect transistor

Abstract: A model is presented for the subthreshold current versus gate voltage of a polycrystalline silicon thin‐film field‐effect transistor. It utilizes the experimentally observed exponential density of states of polycrystalline silicon grain boundaries and is based on an earlier model of M. Shur and M. Hack [J. Appl. Phys. 55, 3831 (1984)] which they applied to hydrogenated amorphous silicon. Experimental subthreshold curves are presented along with the corresponding curves predicted by the model. In addition current activation data are shown to fit the model. The primary fitting parameter is the density of states at the valence band.

A subthreshold current model for GaAs MESFET's

Abstract: A GaAs MESFET model capable of accurately describing currents in the subthreshold region is described. The model is based on the concept of drain-induced barrier lowering (DIBL) together with the reverse-bias Schottky diode conduction. Agreement between measured and calculated data based on this model was excellent.

A Physical Charge-Controlled Model for MOS Transistors

Abstract: As MOS devices scale to submicron lengths, short-channel effects become more pronounced, and an improved transistor model becomes a necessary tool for the VLSI designer [10]. We present a simple, physically based charge-controlled model. The current in the MOS transistor is described in terms of the mobile charge in the channel, and incorporates the physical processes of drift and diffusion. The effect of velocity saturation is included in the drift term. We define a complete set of natural units for velocity, voltage, length, charge, and current. The solution of the dimensionless current-flow equations using these units is a simple continuous expression, equally applicable in the subthreshold, saturation, and "ohmic" regions of transistor operation, and suitable for computer simulation of integrated circuits. The model is in agreement with measurements on short-channel transistors down to 0.35μ channel length.

Hot-carrier drifts in submicrometer p-channel MOSFET's

Abstract: Hot-carrier-induced shifts in p-channel MOSFET operating characteristics have been observed down to drain voltages of - 6 V. Cases are discussed in which p-MOSFET's show up to two orders of magnitude larger degradation than corresponding n-MOSFET's. The shifts include current and threshold voltage increases. From dependences on stress gate voltage, stress drain voltage, time, and substrate current, the hot-carrier origin of the shifts is specified in detail.

A new approach to analytically solving the two-dimensional Poisson's equation and its application in short-channel MOSFET modeling

Abstract: An analytical solution for the potential distribution of the two-dimensional Poisson's equation with the Dirichlet boundary conditions has been obtained for the MOSFET device by using Green's function method and a new transformation technique, in which the effects of source and drain junction curvature and depth are properly considered. Based on the calculated potential distribution, the subthreshold current considering the drain-induced barrier lowering effects has been computed by a simple current equation that considers only the diffusion component with an effective length determined by the potential distribution at the SiO 2 -Si interface. From the calculated subthreshold current, the threshold voltage of the MOSFET's is determined. It has been verified that the dependences of the calculated threshold voltage and subthreshold current on device channel length, drain, and substrate biases are in good agreement with those computed by whole two-dimensional numerical analysis and experimental data.

Hot-carrier induced drain leakage current in n-channel MOSFET

Abstract: Hot-carrier induced drain leakage current in n-channel MOSFET's has been found. Two leakage mechanisms exist at least. The leakage current for one mechanism can be characterized by it, exponential dependence on the drain voltage, approximate proportionality to the stress time, and very small (0.10eV) activation energy. The other mechanism can be characterized by its somewhat ohmic-like dependence on the drain voltage, approximate quadratic dependence on the stress time, and relatively large (0.29eV) activation energy. When stress is imposed by triode-mode operation, the former mechanism is dominant. For pentode-mode operation, the former is followed by the latter. The drain leakage current is observed for conventional, LDD and ALDD (Advanced LDD) structures, although they differ in magnitude. This hot-carrier induced drain leakage current may cause functional failure in DRAM cell or in resistor-load type SRAM cell, while the corresponding degradation in channel conductance may not.

Hysteresis I-V effects in short-channel Silicon MOSFET's

Abstract: Hysteresis in I ds -V ds characteristics is observed at high drain voltages in short-channel silicon MOSFET's biased into the normally off regime, the degree of which depends on the substrate and gate biases. The MOSFET switches at this hysteresis point from subthreshold to space-charge limited current behavior. It is proposed that this hysteresis effect is due to avalanched holes which accumulate at the gate interface, causing a deformation of the potential distribution in the substrate and the triggering of the device into space-charge limited current behavior.

Characterization of GaAs self‐aligned refractory‐gate metal‐semiconductor field‐effect transistor (MESFET) integrated circuits

Abstract: GaAs metal‐semiconductor field‐effect transistors (MESFETs) and other integrated‐circuit elements were characterized by including extensive process test sites on wafers with digital logic and memory circuits. A self‐aligned, refractory‐gate enhancement/depletion (E/D) process was employed which included 47SiF+ channel and source/drain implants, capless arsenic overpressure furnace annealing, WSi0.11 gate metal with in situ sputter cleaning, Ni‐Au‐Ge ohmic contacts, Si3N4 or SiO2 insulation, and Ni‐Au wiring. On‐water threshold voltage standard deviations as low as 31 mV for 1‐μm E‐FETs and 49 mV for 1‐μm D‐FETs were measured using 51‐mm standard semi‐insulating liquid‐encapsulated Czochralski GaAs substrates. Threshold voltage control from wafer to wafer was of order 100 mV. Schottky diode barrier height was about 0.73 eV with an ideality of 1.2, although small self‐aligned Schottky gates often showed excess conduction believed to occur at the gate edges. FET square‐law coefficient, subthreshold leakage, ...

Operation of CMOS devices with a floating well

Abstract: The operation of CMOS devices in an electrically floating well is considered. The impetus for this study is the potential reduction of silicon area consumption and wiring complexity involved in contacting the well diffusion. Theoretical expectations for device behavior are presented and corroborated with experimental data; consideration extends to PMOSFET device characteristics, subthreshold behavior, as well as junction leakage and breakdown voltage. Examination of n-channel devices, in p-wells, indicates that these are more susceptible to floating well effects, as expected. The primary changes in device behavior include generation of substrate current, slight increase in leakage currents, and some degradation in latchup holding voltage. Results indicate that an electrically floating well does not seem to have significant adverse effects on transistor operation.

Impact of Hot Carriers on Dram Circuits

Abstract: Hot carrier stress degradation in MOSFETs is well known but its impact on DRAM circuit functionality has not been thoroughly investigated. In this paper observed DRAM degradation with stress is related to the actual transistor level degradation. It is shown here that the transistor saturation drain current is a good monitor of the DRAM Access Time, while the Precharge Time and the Refresh Time can be related respectively to degradations in the transistor's linear drive current and the saturation region subthreshold current. As concluded in this paper, transistor parameters other than just Vt and gm need to be monitored with hot carrier stress to understand the full impact on DRAM circuit functionality.

A unified analytical model for drain-induced barrier lowering and drain-induced high electric field in a short-channel MOSFET

Abstract: Using the well known El-Mansy-Ko method, a simple solution of the two dimensional Poisson equation is derived at the SiSiO 2 interface for the region bounded by the source and the drain. The solution is valid for long channel as well as short channel MOSFETs. The effect of variable values of the depletion depth is incorporated using the WKB approximation. The solution yields a new model of the subthreshold voltage of a short channel MOSFET. The solution also provides mathematical justification of the intuitive assumptions made by Hsu, Muller and Hu in their paper on punch through currents in short channel MOSFETs. Since the single solution gives both the drain induced high field, DIHF, and the drain induced barrier lowering, DIBL, it also yields an analytical relation between them. The DIBL increases approximately expnentially as E max decreases. The results obtained from this model are in agreement with the numerical simulations and are consistent with the known experimental results.

A Subthreshold Conduction Model for Circuit Simulation of Submicron MOSFET

Abstract: A circuit simulation model for subthreshold conduction of MOSFET is developed. This model employs a novel interpolation scheme to provide smooth transition from the subthreshold region to the above-threshold region. This interpolation scheme ensures that both channel current and its derivatives (or conductances) are smooth. Since an interpolation scheme is used, a simple, independent, and physically based model can be used for the subthreshold and the above-threshold region. The model is applied to subthreshold conduction for submicron MOSFET. It is also successfully installed in a circuit simulation program.

Anomalous Subthreshold Current-Voltage Characteristics of n-Channel

Abstract: The abnormally high slopes of the subthreshold current- voltage characteristics exhibited by n-channel silicon-on-insulator (SOI) MOSFET's are experimentally related to defect density (off-state leakage current) as well as drain voltage and channel length, and a theoretical physical description of the measured relations is presented and supported. The anomalous subthreshold behavior, is attributed analytically to the (floating) body effect due to charging (biasing) by impact ionization at the drain. ECAUSE of the inherent advantages of dielectric isolation in VLSI and in radiation-hardened IC's, silicon-on- insulator (SOI) CMOS technologies are of much interest today. In a recent paper ( 11, Davis et ai. showed that certain n- channel SO1 MOSFET's exhibit abnormally high slopes, or low gate-voltage swings {S = dVGs/d(log ID)), in their subthreshold current-voltage characteristics. After noting that S decreases with decreasing channel length and with increas- ing drain voltage, they associated this abnormality with the kink effect (2), which is normally observed in the suprathresh- old saturation-region characteristics. No physical description of the high subthreshold ID( VGs) slopes was given, however. In this paper we give such a description, supporting it with more comprehensive data that show the effect to be more profound in some cases and that reveal dependences on defect density (off-state leakage current) as well as channel length and drain voltage. While the anomalous subthreshold slopes could be due to significant conduction in the parasitic lateral bipolar transistor (3), we show that they can be described by the (floating) body effect due to charging (biasing) by impact ionization at the drain. Measurements of the body voltage? in addition to the drain current, in the subthreshold region give the physical insight needed to support the description, which in fact can aid the optimal design of SO1 IC's. The anomalous subthreshold behavior is not so severe in the SO1 p-channel transistors, which is commensurate with the lower hole-impact ionization coefficient in silicon. We examined n-channel MOSFET's fabricated in SO1 films produced by implantation of 0 - ions into n-type silicon substrates. The oxygen ions were implanted with an energy of

Steep subthreshold characteristic and enhanced transconductance of fully-recessed oxide (trench) isolated 1/4 µm width MOSFETs

Abstract: This paper describes the dependence of MOSFET gate-controllability on the field isolation scheme. It is found that a fully-recessed oxide (trench) isolated MOSFET has a sharp cutoff characteristic and high transconductance in comparison with a non-recessed one. These features of the fully-recessed oxide MOSFET are due to the crowding of the gate's fringing field at the channel edge. It is also found that the gate and diffused line capacitances for the fully-recessed oxide isolation are small so that high switching speed operation can be expected.

Transistor comparator circuit having split collector feedback hysteresis

Abstract: A comparator circuit responsive to an applied input signal passing through a threshold voltage for providing output signal transitions which comprises circuitry for generating a controllable threshold voltage, comparing circuitry including a first multi-collector transistor which is switched on and off as the input signal passes through the threshold voltage level and which has a collector coupled to the threshold voltage circuitry for sourcing current thereto when the transistor is turned on and the threshold voltage producing circuitry being responsive to the current sourced from the transistor for increasing the magnitude of the threshold voltage, the threshold voltage being supplied to the comparing circuitry.

BJT—MOSFET transconductance comparisons

Abstract: Through normalization it becomes possible to construct curves of considerable generality for comparing the transconductance properties of BJT's and MOSFET's. Three comparisons are given. The first presents transconductance as a function of output current; the second, transconductance divided by output current as a function of input voltage; and the third, transconductance as a function of input voltage. The BJT advantage increases rapidly with output current and (or) input voltage. The curves approach each other under extremely low-level conditions, but appreciable deviations from the simple theory upon which the present analysis is based also occur in the low-level regime--especially deviations connected with subthreshold conduction in the MOSFET, as well as "excess" conduction near but above threshold. For these reasons, the moderate-level portions of the simple-theory comparisons are the most meaningful. Recently developed subthreshold analysis is also used in the second comparison.

A subthreshold model of the narrow-gate effect in MOSFET's

Abstract: The subthreshold softening characteristic of MOSFET's due to the narrow-gate effect has been investigated based on the two-dimensional (2-D) numerical solution of the Poisson equation and device physics. Numerical results taken on stepped-oxide MOSFET's with different gate widths show that a narrower gate width device tends to give higher cut-off voltage. Two parameters account for the softening of the subthreshold characteristics: the subthreshold slope of the drain conductance-gate voltage characteristic and the effective channel width. Both parameters can be extracted easily from the theoretical 2-D computed or experimental drain conductance-gate voltage characteristics. A two-parameter analytical approximation formula for narrow-gate MOSFETs operating in the subthreshold range is thus proposed and tested against exact 2-D numerical results, showing good accuracy. This model is the first one ever reported.

SOI MOSFET in weak inversion and weak accumulation

Abstract: The subthreshold current of silicon-on-insulator (SOI) MOSFETs has been investigated. The importance of the back interface (silicon film/back insulator) on the subthreshold slope factors is emphasised. On the other hand, the dependence of the slope factors on the back insulator thickness is demonstrated and a comparison of the slope factors for the case of the weak inversion and weak accumulation has been carried out.

An analytical threshold voltage model of short-channel MOSFET's with implanted channels

Abstract: An analytical threshold voltage model based on a charge sharing technique is proposed using a new doubly integrable function to simulate the Gaussian channel doping. The model is computationally simple and predicts with reasonable accuracy the various short-channel effects and the anomalous positive threshold shift with shortening channel length.