Showing papers on "Switched capacitor published in 2014"

Hybrid Multilevel Inverter Using Switched Capacitor Units

Abstract: In this paper, two new topologies are proposed for multilevel inverters. The proposed topologies consist of a combination of the conventional series and the switched capacitor inverter units. The proposed topologies reduce the number of switches and isolated dc voltage sources, the variety of the dc voltage source values, and the size and cost of the system in comparison with the conventional topologies. In addition, the proposed topologies can double the input voltage without a transformer. There is no need for complicated methods to balance the capacitor voltage. The simulation and experimental results of single-phase 25- and 17-level inverters are given to prove the correct operation of the proposed topologies.

A step-up switched-capacitor multilevel inverter with self-voltage balancing

Abstract: The objective of this paper is to propose a new inverter topology for a multilevel voltage output. This topology is designed based on a switched capacitor (SC) technique, and the number of output levels is determined by the number of SC cells. Only one dc voltage source is needed, and the problem of capacitor voltage balancing is avoided as well. This structure is not only very simple and easy to be extended to a higher level, but also its gate driver circuits are simplified because the number of active switches is reduced. The operational principle of this inverter and the targeted modulation strategies are presented, and power losses are investigated. Finally, the performance of the proposed multilevel inverter is evaluated with the experimental results of an 11-level prototype inverter.

A Chain Structure of Switched Capacitor for Improved Cell Balancing Speed of Lithium-Ion Batteries

Abstract: Among various active cell balancing circuits, a switched capacitor circuit is promising because it can be implemented with low cost and small size. However, when the switched capacitor is applied in the lithium-ion battery, cell balancing speed is generally slow when the number of batteries is high. Therefore, this paper proposes the chain structure of the switched capacitor to increase balancing speed, particularly among outer cells. In this paper, the cell balancing principle of the conventional switched capacitor is explained, and the reason why slow cell balancing of the switched capacitor is shown in the lithium-ion battery is analyzed. To improve cell balancing speed, two circuits with chain structure are proposed. The balancing performance of the proposed circuits is confirmed by computer simulation, and a comparison between conventional and proposed circuits is presented. The theoretical analysis on the cell balancing speed of conventional structures and the proposed chain structure is also shown in this paper. Experimental tests were carried out to verify the validity of the proposed structures, and the experimental results show an improved balancing performance of the proposed circuit.

A Cascaded Multilevel Inverter Based on Switched-Capacitor for High-Frequency AC Power Distribution System

Abstract: The increase of transmission frequency reveals more merits than low- or medium-frequency distribution among different kinds of power applications. High-frequency inverter serves as source side in high-frequency ac (HFAC) power distribution system (PDS). However, it is complicated to obtain a high-frequency inverter with both simple circuit topology and straightforward modulation strategy. A novel switched-capacitor-based cascaded multilevel inverter is proposed in this paper, which is constructed by a switched-capacitor frontend and H-Bridge backend. Through the conversion of series and parallel connections, the switched-capacitor frontend increases the number of voltage levels. The output harmonics and the component counter can be significantly reduced by the increasing number of voltage levels. A symmetrical triangular waveform modulation is proposed with a simple analog implementation and low modulation frequency comparing with traditional multicarrier modulation. The circuit topology, symmetrical modulation, operation cycles, Fourier analysis, parameter determination, and topology enhancement are examined. An experimental prototype with a rated output frequency of 25 kHz is implemented to compare with simulation results. The experimental results agreed very well with the simulation that confirms the feasibility of proposed multilevel inverter.

A Switched-Capacitor-Based Active-Network Converter With High Voltage Gain

Abstract: The voltage gain of traditional boost converter is limited due to the high current ripple, high voltage stress across active switch and diode, and low efficiency associated with large duty ratio operation. High voltage gain is required in applications, such as the renewable energy power systems with low input voltage. A high step-up voltage gain active-network converter with switched-capacitor technique is proposed in this paper. The proposed converter can achieve high voltage gain without extremely high duty ratio. In addition, the voltage stress of the active switches and output diodes is low. Therefore, low voltage components can be adopted to reduce the conduction loss and cost. The operating principle and steady-state analysis are discussed in detail. A prototype with 20-40-V input voltage, 200-V output voltage, and 200-W output power has been established in the laboratory. Experimental results are given to verify the analysis and advantages of the proposed converter.

An Ultra-Low Power Fully Integrated Energy Harvester Based on Self-Oscillating Switched-Capacitor Voltage Doubler

Abstract: This paper presents a fully integrated energy harvester that maintains >35% end-to-end efficiency when harvesting from a 0.84 mm 2 solar cell in low light condition of 260 lux, converting 7 nW input power from 250 mV to 4 V. Newly proposed self-oscillating switched-capacitor (SC) DC-DC voltage doublers are cascaded to form a complete harvester, with configurable overall conversion ratio from 9× to 23×. In each voltage doubler, the oscillator is completely internalized within the SC network, eliminating clock generation and level shifting power overheads. A single doubler has >70% measured efficiency across 1 nA to 0.35 mA output current ( >10 5 range) with low idle power consumption of 170 pW. In the harvester, each doubler has independent frequency modulation to maintain its optimum conversion efficiency, enabling optimization of harvester overall conversion efficiency. A leakage-based delay element provides energy-efficient frequency control over a wide range, enabling low idle power consumption and a wide load range with optimum conversion efficiency. The harvester delivers 5 nW-5 μW output power with >40% efficiency and has an idle power consumption 3 nW, in test chip fabricated in 0.18 μm CMOS technology.

Level- and Phase-Shifted PWM for Seven-Level Switched-Capacitor Inverter Using Series/Parallel Conversion

Abstract: This paper presents a comparison of two modulation methods for the seven-level switched-capacitor (SC) inverter using series/parallel conversion (SCISPC). The SCISPC is a multilevel inverter which has the less number of switching devices than the conventional multilevel inverters. The level-shifted pulsewidth modulation (PWM) (LS-PWM) was applied to the seven-level SCISPC in the previous research. In this paper, the level- and phase-shifted PWM (LPS-PWM) and the LS-PWM are applied to the seven-level SCISPC, and LPS-PWM is compared with LS-PWM for the seven-level SCISPC. The LPS-PWM has both the characteristics of the phase-shifted PWM (PS-PWM) and the LS-PWM. The voltage reduction during the discharging term of the SCs is reduced by means of the shorter discharging period compared to LS-PWM. The voltage ripple of the capacitors is also reduced, which leads to higher power conversion efficiency. The difference of the two modulation methods is confirmed by the theoretical approach, simulation with PSIM, and circuit experiment.

A Four-level Hybrid-Clamped Converter With Natural Capacitor Voltage Balancing Ability

Abstract: This paper presents a novel four-level hybrid-clamped converter topology which is composed of eight switches and one flying capacitor per phase. The operating principle is introduced and phase-shifted pulse width modulation is used to control this converter. A detailed analysis of the average currents through the flying capacitor and neutral points of the dc-link is presented. Based on the analysis, it can be concluded that the voltages across the flying capacitor and dc-link capacitors can be naturally balanced under ideal and steady-state condition. A low-power three-phase prototype is built up and experimental results are presented to validate the proposed topology and modulation method.

A 0.45–1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS

Abstract: A fully integrated switched capacitor voltage regulator (SCVR) with on-die high density MIM capacitor, distributed across a 14 KB register file (RF) load is demonstrated in 22 nm tri-gate CMOS. The multi-conversion-ratio SCVR provides a wide output voltage range of 0.45-1 V from a fixed input voltage of 1.225 V. It achieves 63-84% conversion efficiency and supports a maximum load current density of 0.88 A/mm2. The area overhead of the dedicated SCVR on the load is 3.6%. Measured data is presented on various performance indices in detail. Subsequent learning on tradeoffs between various factors like capacitance characteristics, conversion efficiency and current density are delineated and, correlated with theoretical estimates. Performance of RF array shows comparable results when powered with the SCVR and the external rail. The all-digital, modular design allows efficient spatial distribution across the load and hence robust power delivery. The extremely fast response times in the order of few nanoseconds is targeted to benefit agile power management. This work evinces voltage regulator technology as a standard homogenous CMOS component, which can proliferate DVFS domains for maximum energy and area benefits.

A Recursive Switched-Capacitor DC-DC Converter Achieving $2^{N}-1$ Ratios With High Efficiency Over a Wide Output Voltage Range

Abstract: A Recursive Switched-Capacitor (RSC) topology is introduced that enables reconfiguration among 2 N -1 conversion ratios while achieving minimal capacitive charge-sharing loss for a given silicon area. All 2 N -1 ratios are realized by strategically interconnecting N 2:1 SC cells either in series, in parallel, or in a stacked configuration such that the number of input and ground connections are maximized in order to minimize cascaded losses. Importantly, all ratios are dynamically reconfigurable without disconnecting a single capacitor, all while ensuring optimal capacitance/conductance relative-sizing. The RSC topology is inherently regular, enabling recursive inter-cell connection and recursive binary-slicing that implement ratio-reconfiguration with minimum complexity and losses. A scalable all-digital binary search controller is employed to perform ratio-reconfiguration among the available 2 N -1 ratios without using any ratio-threshold generation circuitry. To validate the topology, a 4 bit RSC is fully integrated in 0.25 μm bulk CMOS using MIM capacitors, achieving greater than 70% efficiency over a 0.8-2.2 V output voltage range with 85.8% peak-efficiency from a 2.5V input supply. Compared to a co-fabricated three-ratio (1/3, 1/2, 2/3) Series-Parallel SC converter, the RSC achieves a 40.4% larger output operating range (from 0.04 to 2.2 V), and fills the efficiency-drops in-between the three-ratios by 8% with a 940 Ω load.

Series and parallel hybrid switched capacitor networks for ic power delivery

Abstract: Series switches for power delivery. A regulator operated as a current source is arranged in parallel with a switched capacitor divider. A switched capacitor divider is configured in series with a plurality of linear regulators with each regulating one of a plurality of voltage outputs from the switched capacitor divider. In another embodiment, a series switch bridge has a first pair of switches connected in series with a second pair of switches across a voltage input, each switch within a pair of switches is switched in-phase with the other while the first pair of switches is switched out of phase with the second pair of switches. A balancing capacitor is coupled across one switch in both the first and second pair to be in parallel when either of the pair of switches is closed to reduce a charge imbalance between the switches.

Enhanced Differential Power Processor for PV Systems: Resonant Switched-Capacitor Gyrator Converter With Local MPPT

Abstract: This paper introduces an enhanced differential power processor topology and principle of operation for photovoltaic (PV) systems that is based on switched-capacitor technology, featuring local maximum power point tracking (MPPT) capability, zero current switching, high efficiency over wide-operation range, and reduced size. The new converter operates as a voltage-dependent current-source and is regulated by dead-time or frequency control. Local MPPT on the individual PV elements is realized and the operation is demonstrated by simulation and experiments. Differential power processing operation is verified using 150-W prototypes, demonstrating ultimate improvement in the power harvesting capability of above 90% and up to 99% out of the available power in the string, under different insolation levels.

4.6 An 85%-efficiency fully integrated 15-ratio recursive switched-capacitor DC-DC converter with 0.1-to-2.2V output voltage range

Abstract: The growing demand for both performance and battery life in portable consumer electronics requires SoCs and power management circuits to be small, efficient, and dynamically powerful. Dynamic voltage scaling (DVS) can help achieve these goals in load circuits, though generally at the expense of increased DC-DC converter size (through use of external inductors) or loss (through linear regulation). While switched-capacitor (SC) DC-DC converters can offer conversion in small fully integrated form factors [1-5], their efficiencies are only high at discrete ratios between the input and output voltages. To increase an SC converter efficiency across its output voltage range, multiple conversion ratios can be utilized to realize a finer output voltage resolution. For instance, many converters employ a small handful of conversion ratios [1-4]. However, more conversion ratios are generally necessary to achieve high efficiency across the wide output range necessary for DVS, as converter efficiencies can otherwise fall by more than 20% between unloaded ratios [1-4]. Unfortunately, increasing the number of ratios beyond a small handful using standard topologies can significantly increase the number of components, escalating converter complexity and adding losses in the additional switching elements. To overcome this, a successive approximation (SAR) SC topology was proposed in [6] which cascades several 2:1 SC stages to provide a large number of conversion ratios with minimal hardware overhead. However, the linear cascading of stages introduces cascaded losses, limiting overall efficiency. For example, the minimum Rout is more than 30X Rout of a similar ratio Series-Parallel topology using the same silicon area. Additionally, current density is limited to that of a single stage, and capacitance utilization can be low for many conversion ratios.

Method and apparatus for adapting a variable impedance network

Abstract: The present disclosure may include, for example, a tunable capacitor having a decoder for generating a plurality of control signals, and an array of tunable switched capacitors comprising a plurality of fixed capacitors coupled to a plurality of switches. The plurality of switches can be controlled by the plurality of control signals to manage a tunable range of reactance of the array of tunable switched capacitors. Additionally, the array of tunable switched capacitors is adapted to have non-uniform quality (Q) factors. Additional embodiments are disclosed.

23.3 A 3nW fully integrated energy harvester based on self-oscillating switched-capacitor DC-DC converter

Abstract: Recent advances in low-power circuits have enabled mm-scale wireless systems [1] for wireless sensor networks and implantable devices, among other applications Energy harvesting is an attractive way to power such systems due to limited energy capacity of batteries at these form factors However, the same size limitation restricts the amount of harvested power, which can be as low as 10s of nW for mm-scale photovoltaic cells in indoor conditions Efficient DC-DC up-conversion at such low power levels (for battery charging) is extremely challenging and has not yet been demonstrated

Switched-capacitor isolated led driver

Abstract: A switched-capacitor voltage converter which is particularly well-suited for receiving a line voltage from which to drive current through a series of light emitting diodes (LEDs). Input voltage is rectified in a multi-level rectifier network having switched capacitors in an ascending-bank configuration for passing voltages in uniform steps between zero volts up to full received voltage VDC. A regulator section, operating on VDC, comprises switched-capacitor stages of H-bridge switching and flying capacitors. A current controlled oscillator drives the states of the switched-capacitor stages and changes its frequency to maintain a constant current to the load. Embodiments are described for isolating the load from the mains, utilizing an LC tank circuit or a multi-primary-winding transformer.

Analysis and Modeling of a Gain-Boosted N-Path Switched-Capacitor Bandpass Filter

Abstract: The demand of highly-integrated multi-band transceivers has driven the development of blocker-tolerant software-defined radios that can avoid the cost (and loss) of the baluns and SAW filters [1, 2, 3].

Battery Management System—Balancing Modularization Based on a Single Switched Capacitor and Bi-Directional DC/DC Converter with the Auxiliary Battery

Abstract: Lithium-based batteries are considered as the most advanced batteries technology, which can be designed for high energy or high power storage systems. However, the battery cells are never fully identical due to the fabrication process, surrounding environment factors and differences between the cells tend to grow if no measures are taken. In order to have a high performance battery system, the battery cells should be continuously balanced for maintain the variation between the cells as small as possible. Without an appropriate balancing system, the individual cell voltages will differ over time and battery system capacity will decrease quickly. These issues will limit the electric range of the electric vehicle (EV) and some cells will undergo higher stress, whereby the cycle life of these cells will be shorter. Quite a lot of cell balancing/equalization topologies have been previously proposed. These balancing topologies can be categorized into passive and active balancing. Active topologies are categorized according to the active element used for storing the energy such as capacitor and/or inductive component as well as controlling switches or converters. This paper proposes an intelligent battery management system (BMS) including a battery pack charging and discharging control with a battery pack thermal management system. The BMS user input/output interfacing. The battery balancing system is based on battery pack modularization architecture. The proposed modularized balancing system has different equalization systems that operate inside and outside the modules. Innovative single switched capacitor (SSC) control strategy is proposed to balance between the battery cells in the module (inside module balancing, IMB). Novel utilization of isolated bidirectional DC/DC converter (IBC) is proposed to balance between the modules with the aid of the EV auxiliary battery (AB). Finally an experimental step-up has been implemented for the validation of the proposed balancing system.

A Biological-Realtime Neuromorphic System in 28 nm CMOS using Low-Leakage Switched Capacitor Circuits

Abstract: A switched-capacitor (SC) neuromorphic system for closed-loop neural coupling in 28 nm CMOS is presented, occupying 600 um by 600 um. It offers 128 input channels (i.e. presynaptic terminals), 8192 synapses and 64 output channels (i.e. neurons). Biologically realistic neuron and synapse dynam- ics are achieved via a faithful translation of the behavioural equations to SC circuits. As leakage currents significantly affect circuit behaviour at this technology node, dedicated compensation techniques are employed to achieve biological-realtime operation, with faithful reproduction of time constants of several 100 ms at room temperature. Power draw of the overall system is 1.9 mW.

A Novel Quasi-Resonant Bridge Modular Switched-Capacitor Converter With Enhanced Efficiency and Reduced Output Voltage Ripple

Abstract: A novel quasi-resonant bridge modular switched-capacitor converter (BMSCC) is proposed in the paper. The main merit is that its resonant circuit has high stability and simplicity, resulting from the employment of the stray inductance distributed in the circuit as a collective resonant inductor. Accordingly, the current spike during switching operation is removed due to zero-current-switching (ZCS) realization. Another distinct merit is that the proposed converter features symmetric construction. With this kind of construction, the voltage ripple of charge/pump capacitors can be cancelled out with each other and then output voltage ripple will be largely reduced. Thus, it is unnecessary to use a bulky capacitor to reduce output voltage ripple. Compared with conventional SCCs, at the same conversion ratio, the BMSCC with symmetric construction requires fewer switches and capacitors with lower voltage stress, so as to cut the size and cost and promote the power destiny further. It is also noteworthy that the symmetric construction character assures that the two symmetric parts can work independently under a simplified control strategy. In addition, the modular configuration contributes to convenient voltage extension conveniently. The simulation and experimental results of a 100 W prototype with a voltage conversion ratio of eight validate the principle and features of this topology.

Split-phase control: Achieving complete soft-charging operation of a dickson switched-capacitor converter

Abstract: Switched-capacitor (SC) converters are gaining popularity due to their high power density and suitability for on-chip integration. Soft-charging techniques can be used to eliminate the current transient during the phase switching instances, and improve the power density and efficiency of SC converters. In this paper, we propose a split-phase control scheme that enables the Dickson converter to achieve complete soft-charging operation, which is not possible using the conventional two-phase control. An analytical method is extended to understand and design split-phase controlled Dickson converters. The proposed technique and analysis are verified by both simulation and experimental results. An 8-to-1 step-down Dickson converter is built to demonstrate the reduction in output impedance and improvement in efficiency as a result of the split-phase controlled soft-charging operation.

Novel Calibration Method for Switched Capacitor Arrays Enables Time Measurements With Sub-Picosecond Resolution

Abstract: Switched capacitor arrays (SCA) ASICs are becoming more and more popular for the readout of detector signals, since the sampling frequency of typically several gigasamples per second allows excellent pile-up rejection and time measurements. They suffer however from the fact that their sampling bins are not equidistant in time, given by limitations of the chip manufacturing. In the past, this has limited time measurements of optimal signals to standard deviations (σ) of about 4-25 ps in accuracy for the split pulse test, depending on the specific chip. This paper introduces a novel time calibration, which determines the true sampling speed of an SCA. Additionally, for two independently running SCA chips, the achieved time resolution improved to less than 3 ps (σ) independently from the delay for the split pulse test, when simply applying a linear interpolation. When using a more advanced analyzing technique for the split pulse test with a single SCA, this limit is pushed below 1 ps (σ) for delays up to 8 ns. Various test measurements with different boards based on the DRS4 ASIC indicate that the new calibration is stable over time but not over larger temperature variations.

A Family of Dual-Phase-Combined Zero-Current Switching Switched-Capacitor Converters

Abstract: A family of dual-phase-combined resonant switched-capacitor (SC) converters with a similar structure is presented in this paper. Comparing with their conventional single-phase version, each of the proposed dual-phase converters is more than just a switched capacitor but also provides the service of two phases operated in the fully complementary manner. This design provides a more stable output voltage with low ripple and significantly reduces the quantity of switches. These converters therefore have the common features of smaller size, lower cost, and higher power density than the conventional multiphase SC converters. With the zero-current switching technique, the proposed converters also possess high-power conversion efficiency. The detailed analysis of the circuit operation and voltage ripples is presented. Experimental results are also provided to confirm the performance of the new family of converters.

High Power Density Series Resonant Inverter Using an Auxiliary Switched Capacitor Cell for Induction Heating Applications

Abstract: This paper proposes a unique topology of voltage-fed high-frequency series load resonant inverter with a lossless snubber capacitor and an auxiliary switched cell for induction heating appliances. The main objective of this paper is to demonstrate how high power density can be achieved by including a switched capacitor cell with the capacitor-clamped half-bridge zero voltage switching high-frequency inverter circuit using the PWM control scheme. The operation principle of the proposed inverter circuit is based upon an asymmetrical duty cycle pulsewidth modulated (PWM) control scheme. The operating performances of high-frequency ac regulation and power conversion efficiency characteristics are shown through experiments with their soft-switching operating ranges.

4.5 A 2-phase resonant switched-capacitor converter delivering 4.3W at 0.6W/mm 2 with 85% efficiency

Abstract: In this work, we present a 2-phase ReSC converter that operates with supply voltages from 3.6 to 6V, providing compatibility for a range of applications including Li-Ion battery supplies. Figure 4.5.2 shows the power train of the 2-phase ReSC converter. The architecture is similar to the 2:1 SC converters in [2-3], but uses inductance, LX, to resonate with the on-chip flying capacitor, CX. On-chip bypass capacitance, Cbp, is used to filter the output voltage and complete the resonant loop in the energy transfer process. The timing of key signals in converter operation is shown in Fig. 4.5.3. In normal operation at the fundamental resonant frequency, ωo=(LXCX)-1/2, resonant impedance ZX is configured in parallel with Vin-Vout in φ1; in φ2, ZX is configured in parallel with Vout. If there is a voltage difference between Vin-Vout and Vout-GND, voltage VX appears as a square wave at the resonant frequency. In φ1, a positive half wave current flows into ZX, drawing energy from Vin; in φ2, a negative half wave current flows out of ZX, supplying energy to the load. Similar to the SC topology, this process can be modeled as an effective resistance, REFF, the details of which are discussed in [6]. Operation at the fundamental mode provides the lowest achievable REFF, which is approximately RESR·π2/8 for the 2:1 configuration, near the minimum achievable REFF for a comparable SC converter.

A 10-Bit Column-Driver IC With Parasitic-Insensitive Iterative Charge-Sharing Based Capacitor-String Interpolation for Mobile Active-Matrix LCDs

Abstract: This paper presents a 10-bit column driver IC for active-matrix LCDs, with a proposed iterative charge-sharing based (ICSB) capacitor-string that interpolates two output voltages from a resistor-string DAC. Iterative mode change between a capacitive voltage division mode and a charge sharing mode in the ICSB capacitor-string interpolation suppresses the effect of mismatches between capacitors and that of parasitic capacitances; thus, a highly linear capacitor sub-DAC is realized. In addition, the area-sharing layout technique, which stacks the interpolation capacitor-string on top of the R-DAC area, reduces the driver channel size and extends the bit resolution of the gamma-corrected nonlinear main R-DAC. Consequently, the proposed ICSB capacitor-string interpolation scheme provides highly uniform channel performance by passively dividing the coarse voltages from the global resistor-string DAC with high area efficiency, and more effective bit resolution for nonlinear gamma correction. The prototype column driver IC was implemented using a 0.11-μm CMOS process. The area occupation of the DAC and buffer amplifier per channel is only 188 × 15 μm2, and the static power consumption is 0.9 μA/channel with no additional static power dissipation for the interpolation. The measured maximum DNL and INL are 0.25 LSB and 0.43 LSB, respectively. The measured maximum inter-channel DVO is 5.6 mV. The proposed chip achieves state-of-the-art performance in terms of chip size and channel-to-channel uniformity.

An Optimum Design for Integrated Switched-Capacitor Dickson Charge Pump Multipliers With Area Power Balance

Abstract: This letter expands upon an optimum design of integrated switched-capacitor Dickson charge pump multipliers for minimizing the power, which considers the parasitic capacitance of both the top and bottom plates of pump capacitors. This letter also discusses an optimum design with area power balance, and suggests that the number of stages should be e NMIN, where e is 1.5-1.7 and NMIN is the minimum number of stages required to meet the condition that the output current is zero at a given output voltage.

Efficiency Characterization and Impedance Modeling of a Multilevel Switched-Capacitor Converter Using Pulse Dropping Switching Scheme

Abstract: A pulse dropping switching technique (PDT) has been presented in this paper to accomplish variable conversion ratio (CR) in a multilevel modular capacitor-clamped dc-dc converter in the step-up conversion mode. The switching pattern is generated by comparing a triangular wave with a rectangular wave, and a proper output voltage regulation can be obtained by controlling the relative frequency and amplitude of these two waveforms. A state-space modeling technique has been applied here to estimate the variation in equivalent output resistance (EOR) for different operating conditions of the PDT. The EOR can be varied in a wide range without changing the operating frequency of the converter, and thereby the PDT enhances the degrees of freedom to accomplish voltage regulation in a two-phase switched-capacitor converter. Slow-switching limit of the converter has been derived to define the boundary of the EOR. Different challenges and limitations of the proposed modulation scheme has been discussed in detail, and the proposed analysis has been verified by comparing the analytical expressions with the simulation and experimental results for different switching frequencies, modulation indices, and number of active modules. In addition, variations in the CR, efficiency and ripple voltage for different number of active modules and switching conditions have been described in detail.