John Iacoponi

TL;DR: A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate.

TL;DR: In this article, the etch stop layer formed on the upper surfaces of the sidewall spacers and the final gate structure of a transistor was constructed to form a conductive contact that is coupled to a contact region of the transistor.

TL;DR: In this paper, various methods of forming isolation structures on FinFETs and other semiconductor devices, and the resulting devices that have such isolation structures are discussed, including forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define a fin for a fin, forming a layer of insulating material in the trenches, and performing a heating process in an oxidizing ambient.

TL;DR: In this article, the authors describe a method for forming an integrated circuit that includes forming a sacrificial mandrel overlying a base substrate, and then forming a first dielectric layer overlying the base substrate and is conformal to at least a portion of the upper portion of sidewall spacers.

TL;DR: In this paper, a 10nm CMOS platform technology for low power and high performance applications with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm was reported in the FinFET technology on both bulk and SOI substrates.