C
Christopher J. Waskiewicz
Researcher at IBM
Publications - 35
Citations - 395
Christopher J. Waskiewicz is an academic researcher from IBM. The author has contributed to research in topics: Layer (electronics) & Multiple patterning. The author has an hindex of 9, co-authored 32 publications receiving 370 citations.
Papers
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Proceedings ArticleDOI
A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI
Kang-ill Seo,Balasubramanian S. Pranatharthi Haran,Dinesh Gupta,Dechao Guo,Theodorus E. Standaert,Ruilong Xie,H. Shang,E. Alptekin,D.I. Bae,Geum-Jong Bae,Carol Boye,H. Cai,D. Chanemougame,Robin Chao,Kangguo Cheng,Jin Cho,Kisik Choi,B. Hamieh,J. G. Hong,Terence B. Hook,L. Jang,Ju-Hwan Jung,R. Jung,Deok-Hyung Lee,B. Lherron,R. Kambhampati,Bomsoo Kim,Hoon Kim,K. Kim,Tae-Chan Kim,S.-B. Ko,Fee Li Lie,Derrick Liu,H. Mallela,Erin Mclellan,Sanjay Mehta,P. Montanini,M. Mottura,J. Nam,S. Nam,F. Nelson,Injo Ok,Chanro Park,Young-Kwan Park,Abhijeet Paul,Christopher Prindle,Ravikumar Ramachandran,Muthumanickam Sankarapandian,V. Sardesai,Andreas Scholze,Soon-Cheon Seo,Jeffrey C. Shearer,Richard G. Southwick,Raghavasimhan Sreenivasan,S. Stieg,Jay W. Strane,Xiao Sun,Min Gyu Sung,Charan V. V. S. Surisetty,Gen Tsutsui,Neeraj Tripathi,Reinaldo A. Vega,Christopher J. Waskiewicz,M. Weybright,C.-C. Yeh,Huiming Bu,Sean D. Burns,Donald F. Canaperi,M. Celik,Matthew E. Colburn,Hemanth Jagannathan,S. Kanakasabaphthy,Walter Kleemeier,Lars W. Liebmann,D. McHerron,Philip J. Oldiges,Vamsi Paruchuri,Terry A. Spooner,James H. Stathis,R. Divakaruni,T. Gow,John Iacoponi,J. Jenq,R. Sampson,Mukesh Khare +84 more
TL;DR: A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate.
Patent
BEOL vertical fuse formed over air gap
TL;DR: In this paper, a method of forming an electrical device that includes forming a first level including an array of metal lines, wherein an air gap is positioned between the adjacent metal lines and conductive material is formed within the trenches.
Patent
Method of forming active devices of different gatelengths using lithographic printed gate images of same length
TL;DR: In this article, a method for simultaneously patterning features having a first width in a first portion such as a logic portion of an integrated circuit, and having a second width in an array portion, is presented.
Journal ArticleDOI
BEOL Cu CMP Process Evaluation for Advanced Technology Nodes
Kunaljeet Tanwar,Donald F. Canaperi,Michael F. Lofaro,Wei-Tsu Tseng,Raghuveer R. Patlolla,Christopher J. Penny,Christopher J. Waskiewicz +6 more
Proceedings ArticleDOI
EUV lithography at the 22nm technology node
Obert Wood,Chiew-seng Koay,Karen Petrillo,Hiroyuki Mizuno,Sudhar Raghunathan,John C. Arnold,D. Horak,Martin Burkhardt,Gregory McIntyre,Yunfei Deng,Bruno La Fontaine,Uzodinma Okoroanyanwu,Tom Wallow,Guillaume Landie,Theodorus E. Standaert,Sean D. Burns,Christopher J. Waskiewicz,H. Kawasaki,Chen Jim C,Matthew E. Colburn,Balasubramanian S. Haran,S. Fan,Yunpeng Yin,Christian Holfeld,Jens Techel,Jan-Hendrik Peters,Sander Bouten,Brian Lee,Bill Pierson,Bart Kessels,Robert Routh,Kevin Cummings +31 more
TL;DR: In this article, the authors evaluate the readiness of extreme ultraviolet (EUV) lithography for insertion into production at the 15 nm technology node by integrating it into standard semiconductor process flows because they believe that device integration exercises provide the truest test of technology readiness and highlight the remaining critical issues.