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Kang-ill Seo
Researcher at Samsung
Publications - 52
Citations - 847
Kang-ill Seo is an academic researcher from Samsung. The author has contributed to research in topics: Layer (electronics) & Substrate (printing). The author has an hindex of 17, co-authored 49 publications receiving 805 citations. Previous affiliations of Kang-ill Seo include Seoul National University & Stanford University.
Papers
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Journal ArticleDOI
Surface Charge Density of Unpassivated and Passivated Metal-Catalyzed Silicon Nanowires
TL;DR: In this article, the surface-charge density of a nanowire covered with native oxide is about 2 X 10 12 cm -2 ; the density appears to decrease by a factor of two to four when the native oxide was replaced by a high-quality thermally grown oxide, with further improvement possible.
Proceedings ArticleDOI
A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI
Kang-ill Seo,Balasubramanian S. Pranatharthi Haran,Dinesh Gupta,Dechao Guo,Theodorus E. Standaert,Ruilong Xie,H. Shang,E. Alptekin,D.I. Bae,Geum-Jong Bae,Carol Boye,H. Cai,D. Chanemougame,Robin Chao,Kangguo Cheng,Jin Cho,Kisik Choi,B. Hamieh,J. G. Hong,Terence B. Hook,L. Jang,Ju-Hwan Jung,R. Jung,Deok-Hyung Lee,B. Lherron,R. Kambhampati,Bomsoo Kim,Hoon Kim,K. Kim,Tae-Chan Kim,S.-B. Ko,Fee Li Lie,Derrick Liu,H. Mallela,Erin Mclellan,Sanjay Mehta,P. Montanini,M. Mottura,J. Nam,S. Nam,F. Nelson,Injo Ok,Chanro Park,Young-Kwan Park,Abhijeet Paul,Christopher Prindle,Ravikumar Ramachandran,Muthumanickam Sankarapandian,V. Sardesai,Andreas Scholze,Soon-Cheon Seo,Jeffrey C. Shearer,Richard G. Southwick,Raghavasimhan Sreenivasan,S. Stieg,Jay W. Strane,Xiao Sun,Min Gyu Sung,Charan V. V. S. Surisetty,Gen Tsutsui,Neeraj Tripathi,Reinaldo A. Vega,Christopher J. Waskiewicz,M. Weybright,C.-C. Yeh,Huiming Bu,Sean D. Burns,Donald F. Canaperi,M. Celik,Matthew E. Colburn,Hemanth Jagannathan,S. Kanakasabaphthy,Walter Kleemeier,Lars W. Liebmann,D. McHerron,Philip J. Oldiges,Vamsi Paruchuri,Terry A. Spooner,James H. Stathis,R. Divakaruni,T. Gow,John Iacoponi,J. Jenq,R. Sampson,Mukesh Khare +84 more
TL;DR: A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate.
Journal ArticleDOI
Improvement in High- $k$ $(hboxHfO_2/hboxSiO_2)$ Reliability by Incorporation of Fluorine
TL;DR: In this article, the authors demonstrate that negative bias temperature instability of high-k gate dielectric stacks can be improved by incorporating fluorine and engineering its concentration depth profile with respect to HfO2/SiO2 interface.
Proceedings ArticleDOI
Highly manufacturable 7nm FinFET technology featuring EUV lithography for low power and high performance applications
Dae-Won Ha,C. Yang,J. H. Lee,S.Y. Lee,Sun-Ghil Lee,Kang-ill Seo,Hansu Oh,E. C. Hwang,S. W. Do,S. C. Park,M.-C. Sun,D.H. Kim,Junha Lee,M. I. Kang,S.-S. Ha,D. Y. Choi,Hwichan Jun,Hong-jae Shin,Yun-gi Kim,C. W. Moon,Young-Joon Cho,S. H. Park,Young-Jae Son,Jeong-Heon Park,Byeong Chan Lee,Cheolkyu Kim,Y. M. Oh,Jintaek Park,Sei-jin Kim,Myeong-Cheol Kim,Ki-Hyun Hwang,S. W. Nam,Shigenobu Maeda,Dae-Youn Kim,M. S. Liang,E. S. Jung +35 more
TL;DR: In this article, the 4.7nm CMOS FinFET technology featuring EUV lithography, 4th gen. dual Fin and 2nd gen. multi-eWF gate stack is presented, providing 20% faster speed or consuming 35% less total power over 10nm technology.
Journal ArticleDOI
Chemical states and electronic structure of a HfO(-2) / Ge(001) interface
TL;DR: In this article, the chemical bonding structure and valence band alignment at the HfO{sub 2}/Ge (001) interface were investigated by systematically probing various core level spectra as well as valence bands spectra using soft x-rays at the Stanford Synchrotron Radiation Laboratory.