V
V. Sardesai
Researcher at IBM
Publications - 3
Citations - 123
V. Sardesai is an academic researcher from IBM. The author has contributed to research in topics: CMOS & Silicon on insulator. The author has an hindex of 3, co-authored 3 publications receiving 113 citations.
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Proceedings ArticleDOI
A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI
Kang-ill Seo,Balasubramanian S. Pranatharthi Haran,Dinesh Gupta,Dechao Guo,Theodorus E. Standaert,Ruilong Xie,H. Shang,E. Alptekin,D.I. Bae,Geum-Jong Bae,Carol Boye,H. Cai,D. Chanemougame,Robin Chao,Kangguo Cheng,Jin Cho,Kisik Choi,B. Hamieh,J. G. Hong,Terence B. Hook,L. Jang,Ju-Hwan Jung,R. Jung,Deok-Hyung Lee,B. Lherron,R. Kambhampati,Bomsoo Kim,Hoon Kim,K. Kim,Tae-Chan Kim,S.-B. Ko,Fee Li Lie,Derrick Liu,H. Mallela,Erin Mclellan,Sanjay Mehta,P. Montanini,M. Mottura,J. Nam,S. Nam,F. Nelson,Injo Ok,Chanro Park,Young-Kwan Park,Abhijeet Paul,Christopher Prindle,Ravikumar Ramachandran,Muthumanickam Sankarapandian,V. Sardesai,Andreas Scholze,Soon-Cheon Seo,Jeffrey C. Shearer,Richard G. Southwick,Raghavasimhan Sreenivasan,S. Stieg,Jay W. Strane,Xiao Sun,Min Gyu Sung,Charan V. V. S. Surisetty,Gen Tsutsui,Neeraj Tripathi,Reinaldo A. Vega,Christopher J. Waskiewicz,M. Weybright,C.-C. Yeh,Huiming Bu,Sean D. Burns,Donald F. Canaperi,M. Celik,Matthew E. Colburn,Hemanth Jagannathan,S. Kanakasabaphthy,Walter Kleemeier,Lars W. Liebmann,D. McHerron,Philip J. Oldiges,Vamsi Paruchuri,Terry A. Spooner,James H. Stathis,R. Divakaruni,T. Gow,John Iacoponi,J. Jenq,R. Sampson,Mukesh Khare +84 more
TL;DR: A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate.
Proceedings ArticleDOI
High performance bulk planar 20nm CMOS technology for low power mobile applications
Huiling Shang,S. Jain,E. Josse,E. Alptekin,M.H. Nam,Seung-Kwon Kim,Kyung-hwan Cho,Il-Ryong Kim,Y. Liu,X. Yang,X. Wu,J. Ciavatti,Nam-Sung Kim,R. Vega,L. Kang,H.V. Meer,Srikanth Samavedam,M. Celik,S. Soss,Henry K. Utomo,Ravikumar Ramachandran,W. Lai,V. Sardesai,C. Tran,Jung-Geun Kim,Y.H. Park,W.L. Tan,T. Shimizu,R. Joy,Jay W. Strane,Keith H. Tabakman,Frederic Lalanne,P. Montanini,Katherina Babich,Jin Bum Kim,L. Economikos,W. Cote,C. Reddy,Michael P. Belyansky,R. Arndt,U. Kwon,Keith Kwong Hon Wong,Dinesh Koli,D. Levedakis,J.W. Lee,J. Muncy,Siddarth A. Krishnan,Dominic J. Schepis,X. Chen,Bomi Kim,C. Tian,Barry Linder,Eduard A. Cartier,Vijay Narayanan,Greg Northrop,O. Menut,J. Meiring,Alvin G. Thomas,M. Aminpur,Park Sejun,K.Y. Lee,B.Y. Kim,S. H. Rhee,B. Hamieh,Ravi Prakash Srivastava,R. Koshy,C. Goldberg,M. Pallachalil,M. Chae,A. Ogino,T. Watanabe,M. Oh,H. Mallela,D. Codi,Pierre Malinge,M. Weybright,Randy W. Mann,Anurag Mittal,M. Eller,S. Lian,Yujun Li,R. Divakaruni,Scott J. Bukofsky,Jedon Kim,J. Sudijono,W. Neumueller,F. Matsuoka,R. Sampson +87 more
TL;DR: A high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate process, strain engineering, 64nm metal pitch & ULK dielectrics, which offers 0.55X density scaling and enables significant frequency improvement at lower standby power.
Proceedings ArticleDOI
10nm FINFET technology for low power and high performance applications
Dechao Guo,H. Shang,Kang-ill Seo,Balasubramanian S. Pranatharthi Haran,Theodorus E. Standaert,Dinesh Gupta,E. Alptekin,D.I. Bae,Geum-Jong Bae,D. Chanemougame,Kangguo Cheng,Jin Cho,B. Hamieh,J. G. Hong,T. Hook,Ju-Hwan Jung,R. Kambhampati,Bomsoo Kim,Hoon Kim,K. Kim,Tae-Chan Kim,Derrick Liu,H. Mallela,P. Montanini,M. Mottura,S. Nam,Injo Ok,Young-Kwan Park,Abhijeet Paul,Christopher Prindle,Ravikumar Ramachandran,V. Sardesai,Andreas Scholze,Soon-Cheon Seo,Richard G. Southwick,Jay W. Strane,Xiao Sun,Gen Tsutsui,Neeraj Tripathi,Reinaldo A. Vega,M. Weybright,Ruilong Xie,C.-C. Yeh,Huiming Bu,Sean D. Burns,Donald F. Canaperi,M. Celik,Matthew E. Colburn,Hemanth Jagannathan,S. Kanakasabaphthy,Walter Kleemeier,Lars W. Liebmann,D. McHerron,Philip J. Oldiges,Vamsi Paruchuri,Terry A. Spooner,James H. Stathis,R. Divakaruni,T. Gow,John Iacoponi,J. Jenq,R. Sampson,W. Yang,Mukesh Khare +63 more
TL;DR: In this paper, a 10nm CMOS platform technology for low power and high performance applications with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm was reported in the FinFET technology on both bulk and SOI substrates.