K
K. Kim
Researcher at Samsung
Publications - 13
Citations - 476
K. Kim is an academic researcher from Samsung. The author has contributed to research in topics: Transistor & X-ray photoelectron spectroscopy. The author has an hindex of 9, co-authored 13 publications receiving 463 citations.
Papers
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Proceedings ArticleDOI
The breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor(RCAT) for 88 nm feature size and beyond
Joonsuk Kim,Chang-Sub Lee,S. Kim,I.B. Chung,Yong-lack Choi,Byung-lyul Park,J.W. Lee,D.I. Kim,Young-Nam Hwang,D.S. Hwang,H.K. Hwang,Jong Moon Park,D.H. Kim,N.J. Kang,Mann Ho Cho,Myung Yung Jeong,Hoonki Kim,Jung-In Han,S.Y. Kim,Byeong Yun Nam,Hyun-Mog Park,S.H. Chung,J. H. Lee,Jintaek Park,H.S. Kim,Yang-Keun Park,K. Kim +26 more
TL;DR: In this paper, a Recess-Channel-Array-Transistor (RCAT) with 88 nm feature size has been developed for DRAM with a gate length of 75 nm and channel depth of 150 nm.
Proceedings ArticleDOI
Highly Reliable 256Mb PRAM with Advanced Ring Contact Technology and Novel Encapsulating Technology
Yoon-Jong Song,Kyung-Chang Ryoo,Young-Nam Hwang,Changwook Jeong,D. Lim,S.O. Park,Jung-Geun Kim,S.Y. Lee,J.H. Kong,S.J. Ahn,J.M. Park,Jae-joon Oh,Yong-chul Oh,Jun-Ho Shin,Y. Fai,Gwan-Hyeob Koh,Gitae Jeong,Rak-Hwan Kim,Hyun-Seok Lim,I.S. Park,H.S. Jeong,K. Kim +21 more
TL;DR: In this article, an advanced ring type and encapsulating scheme was developed to fabricate highly manufacturable and reliable 256Mb PRAM, in which core dielectrics were optimized for cell contact CMP process and relatively high set resistance was stabilized from encapsulating Ge2Sb2Te5 (GST) stack with blocking layers.
Proceedings ArticleDOI
A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI
Kang-ill Seo,Balasubramanian S. Pranatharthi Haran,Dinesh Gupta,Dechao Guo,Theodorus E. Standaert,Ruilong Xie,H. Shang,E. Alptekin,D.I. Bae,Geum-Jong Bae,Carol Boye,H. Cai,D. Chanemougame,Robin Chao,Kangguo Cheng,Jin Cho,Kisik Choi,B. Hamieh,J. G. Hong,Terence B. Hook,L. Jang,Ju-Hwan Jung,R. Jung,Deok-Hyung Lee,B. Lherron,R. Kambhampati,Bomsoo Kim,Hoon Kim,K. Kim,Tae-Chan Kim,S.-B. Ko,Fee Li Lie,Derrick Liu,H. Mallela,Erin Mclellan,Sanjay Mehta,P. Montanini,M. Mottura,J. Nam,S. Nam,F. Nelson,Injo Ok,Chanro Park,Young-Kwan Park,Abhijeet Paul,Christopher Prindle,Ravikumar Ramachandran,Muthumanickam Sankarapandian,V. Sardesai,Andreas Scholze,Soon-Cheon Seo,Jeffrey C. Shearer,Richard G. Southwick,Raghavasimhan Sreenivasan,S. Stieg,Jay W. Strane,Xiao Sun,Min Gyu Sung,Charan V. V. S. Surisetty,Gen Tsutsui,Neeraj Tripathi,Reinaldo A. Vega,Christopher J. Waskiewicz,M. Weybright,C.-C. Yeh,Huiming Bu,Sean D. Burns,Donald F. Canaperi,M. Celik,Matthew E. Colburn,Hemanth Jagannathan,S. Kanakasabaphthy,Walter Kleemeier,Lars W. Liebmann,D. McHerron,Philip J. Oldiges,Vamsi Paruchuri,Terry A. Spooner,James H. Stathis,R. Divakaruni,T. Gow,John Iacoponi,J. Jenq,R. Sampson,Mukesh Khare +84 more
TL;DR: A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate.
Proceedings ArticleDOI
A 64-Cell NAND Flash Memory with Asymmetric S/D Structure for Sub-40nm Technology and Beyond
Ki-Kwan Park,Jung-Dal Choi,Jong-Sun Sel,V. Kim,Chang-seok Kang,Yu-gyun Shin,U. Roh,J.M. Park,Jang-Sik Lee,Jaesung Sim,Sanghun Jeon,Chang-Hyun Lee,K. Kim +12 more
TL;DR: A new 64-cell NAND flash memory with asymmetric S/D (Source/Drain) structure for sub-40nm node technology and beyond has been successfully developed to suppress short channel effect in NAND memory cell.
Proceedings ArticleDOI
Tungsten silicide/titanium nitride compound gate for submicron CMOSFET
K. Kim,L.G. Kang,T.S. Park,Yoo-Cheol Shin,Jong-Woo Park,C.J. Lee,C.G. Hwang,D. Chin,Y.E. Park +8 more
TL;DR: In this article, a WSi2/TiN compound-gate MOSFET with a near-midgap work function ranging from 4.63 to 4.75 eV and low resistivity is presented.