Proceedings ArticleDOI
A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI
Kang-ill Seo,Balasubramanian S. Pranatharthi Haran,Dinesh Gupta,Dechao Guo,Theodorus E. Standaert,Ruilong Xie,H. Shang,E. Alptekin,D.I. Bae,Geum-Jong Bae,Carol Boye,H. Cai,D. Chanemougame,Robin Chao,Kangguo Cheng,Jin Cho,Kisik Choi,B. Hamieh,J. G. Hong,Terence B. Hook,L. Jang,Ju-Hwan Jung,R. Jung,Deok-Hyung Lee,B. Lherron,R. Kambhampati,Bomsoo Kim,Hoon Kim,K. Kim,Tae-Chan Kim,S.-B. Ko,Fee Li Lie,Derrick Liu,H. Mallela,Erin Mclellan,Sanjay Mehta,P. Montanini,M. Mottura,J. Nam,S. Nam,F. Nelson,Injo Ok,Chanro Park,Young-Kwan Park,Abhijeet Paul,Christopher Prindle,Ravikumar Ramachandran,Muthumanickam Sankarapandian,V. Sardesai,Andreas Scholze,Soon-Cheon Seo,Jeffrey C. Shearer,Richard G. Southwick,Raghavasimhan Sreenivasan,S. Stieg,Jay W. Strane,Xiao Sun,Min Gyu Sung,Charan V. V. S. Surisetty,Gen Tsutsui,Neeraj Tripathi,Reinaldo A. Vega,Christopher J. Waskiewicz,M. Weybright,C.-C. Yeh,Huiming Bu,Sean D. Burns,Donald F. Canaperi,M. Celik,Matthew E. Colburn,Hemanth Jagannathan,S. Kanakasabaphthy,Walter Kleemeier,Lars W. Liebmann,D. McHerron,Philip J. Oldiges,Vamsi Paruchuri,Terry A. Spooner,James H. Stathis,R. Divakaruni,T. Gow,John Iacoponi,J. Jenq,R. Sampson,Mukesh Khare +84 more
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TLDR
A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate.Abstract:
A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um
2
SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limit. Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.read more
Citations
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Journal ArticleDOI
ASAP7: A 7-nm finFET predictive process design kit
Lawrence T. Clark,Vinay Vashishtha,Lucian Shifren,Aditya Gujja,Saurabh Sinha,Brian Cline,Chandarasekaran Ramamurthy,Greg Yeric +7 more
TL;DR: A high density, low-power standard cell architecture, developed using design/technology co-optimization (DTCO), as well as example SRAM cells are shown, and the PDK transistor electrical assumptions are explained, as are the FEOL and BEOL design rules.
Journal ArticleDOI
Carbon nanotube transistors scaled to a 40-nanometer footprint
TL;DR: A p-channel transistor scaled to such an extremely small dimension is reported on, built on one semiconducting carbon nanotube, which occupies less than half the space of leading silicon technologies, while delivering a significantly higher pitch-normalized current density.
Journal ArticleDOI
Challenges and Limitations of CMOS Scaling for FinFET and Beyond Architectures
TL;DR: In this paper, the authors investigated the scaling trends of FinFET architecture, with focus on Front-End-of-Line (FEOL) and Middle-of Line (MOL) device parameters, and concluded that the combined requirements of device electrostatics together with the demands on contact resistance presents a Contacted-Gate-Pitch (CGP) scaling limit for horizontal-transport FETs.
Journal ArticleDOI
Vertical, electrolyte-gated organic transistors: continuous operation in the MA/cm$^2$ regime and use as low-power artificial synapses
TL;DR: In this article, a novel vertical field effect transistor design with a channel length of only 40 nm and a footprint of 2 x 80 x 80 nm$^2, high electrical performance with organic polymers can be realized when using electrolyte gating.
Journal ArticleDOI
ITRS lithography roadmap: 2015 challenges
Mark Neisser,Stefan Wurm +1 more
TL;DR: In the same time frame, alternative and/or complementary technologies to EUV have made considerable progress as discussed by the authors, such as Directed Self-Assembly (DSA), NIL, and Maskless Lattice Patterning (MLS).
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