D.I. Bae

TL;DR: A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate.

TL;DR: For the first time, multi-level NAND flash memories with a 63 nm design rule were developed successfully using charge trapping memory cells of Si/SiO2/SiN/Al2O3/TaN (TANOS) as mentioned in this paper.

TL;DR: An 8 Gb multi-level NAND flash memory is fabricated in a 63 nm CMOS technology with shallow trench isolation and performance improves to 4.4 MB/s by using the 2/spl times/ program mode and by decreasing the cycle time from 50 ns to 30 ns.

TL;DR: In this article, a bottom oxidation through STI (BOTS) was proposed to enable the fabrication of dielectric isolated FinFETs on bulk substrates by bottom oxidation, achieving competitive performance with effective drive currents of I eff (N/P) = 621/453 μA/μm at I off = 10 nA/m at V DD = 0.8 V.

TL;DR: In this paper, the further oxidization of the as-deposited TaO x films was carried out with the treatment of oxygen plasma, and then Pt/TaO x /Pt devices with a diameter of 200μm were fabricated using magnetron sputtering.