https://cyberleninka.org/article/n/1380904.pdf

ASAP7: A 7-nm finFET predictive process design kit

The International Technology Roadmap for Semiconductors challenges the device research community to reduce the transistor footprint containing all components to 40 nanometers within the next decade. We report on a p-channel transistor scaled to such an extremely small dimension. Built on one semiconducting carbon nanotube, it occupies less than half the space of leading silicon technologies, while delivering a significantly higher pitch-normalized current density—above 0.9 milliampere per micrometer at a low supply voltage of 0.5 volts with a subthreshold swing of 85 millivolts per decade. Furthermore, we show transistors with the same small footprint built on actual high-density arrays of such nanotubes that deliver higher current than that of the best-competing silicon devices under the same overdrive, without any normalization. We achieve this using low-resistance end-bonded contacts, a high-purity semiconducting carbon nanotube source, and self-assembly to pack nanotubes into full surface-coverage aligned arrays.

https://science.sciencemag.org/content/sci/356/6345/1369.full.pdf

Carbon nanotube transistors scaled to a 40-nanometer footprint

Scaling trends of FinFET architecture, with focus on Front-End-of-Line (FEOL), and Middle-of-Line (MOL) device parameters, is systematically investigated. It is concluded that the combined requirements of device electrostatics together with the demands on contact resistance, presents a Contacted-Gate-Pitch (CGP) scaling limit for horizontal-transport FETs. FET drive is expected to significantly degrade below this CGP ~ 40 nm as a result. Good agreement between hardware data and TCAD simulations is achieved and employed to estimate the contact resistance values for aggressively scaled FinFETs. These observations show that FinFETs scaled below CGP of 40 nm will require the contact resistivity (ρ
 C
) of ~8 × 10
 -10
 Ω-cm
 2
, while fully ohmic contacts i.e., ρ
 C
 of ~1 × 10
 -10
 Ω-cm
 2
 will be required if FinFETs are to extend performance below CGP of 30 nm. Ultimately, transition to new device architectures in which contact area is independent of CGP and/or Fin-Pitch will be necessary.

Challenges and Limitations of CMOS Scaling for FinFET and Beyond Architectures

Organic semiconductors are usually not thought to show outstanding performance in highly-integrated, sub 100 nm transistors. Consequently, single-crystalline materials such as SWCNTs, MoS2 or inorganic semiconductors are the material of choice at these nanoscopic dimensions. Here, we show that using a novel vertical field-effect transistor design with a channel length of only 40 nm and a footprint of 2 x 80 x 80 nm$^2$, high electrical performance with organic polymers can be realized when using electrolyte gating. Our organic transistors combine high on-state current densities of above 3 MA/cm$^2$, on/off current modulation ratios of up to 108 and large transconductances of up to 5000 S/m. Given the high on-state currents at yet large on/off ratios, our novel structures also show promise for use in artificial neural networks, where they could operate as memristive devices with sub 100 fJ energy usage.

Vertical, electrolyte-gated organic transistors: continuous operation in the MA/cm$^2$ regime and use as low-power artificial synapses

Abstract In the past few years, novel methods of patterning have made considerable progress. In 2011, extreme ultraviolet (EUV) lithography was the front runner to succeed optical lithography. However, although EUV tools for pilot production capability have been installed, its high volume manufacturing (HVM) readiness continues to be gated by productivity and availability improvements taking longer than expected. In the same time frame, alternative and/or complementary technologies to EUV have made progress. Directed self-assembly (DSA) has demonstrated improved defectivity and progress in integration with design and pattern process flows. Nanoimprint improved performance considerably and is pilot production capable for memory products. Maskless lithography has made progress in tool development and could have an α tool ready in the late 2015 or early 2016. But they all have to compete with multiple patterning. Quadruple patterning is already demonstrated and can pattern lines and spaces down to close to 10-nm half pitch. The other techniques have to do something better than quadruple patterning does to be chosen for implementation. DSA and NIL promise a lower cost. EUV promises a simpler and shorter process and the creation of 2-D patterns more easily with much reduced complexity compared to multiple patterning. Maskless lithography promises to make chip personalization easy and to be particularly cost effective for low-volume chip designs. Decision dates for all of the technologies are this year or next year.

https://www.degruyter.com/downloadpdf/j/aot.2015.4.issue-4/aot-2015-0036/aot-2015-0036.xml

ITRS lithography roadmap: 2015 challenges

A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um
 2
 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limit. Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

In this paper, we present a 10nm CMOS platform technology for low power and high performance applications with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrates. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limits. Multi-workfunction (MWF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by Random Dopant Fluctuation (RDF) from channel dopants.

S. Kanakasabaphthy

Papers

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

10nm FINFET technology for low power and high performance applications