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Massoud Pedram

Researcher at University of Southern California

Publications -  812
Citations -  25236

Massoud Pedram is an academic researcher from University of Southern California. The author has contributed to research in topics: Energy consumption & CMOS. The author has an hindex of 77, co-authored 780 publications receiving 23047 citations. Previous affiliations of Massoud Pedram include University of California, Berkeley & Syracuse University.

Papers
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Journal ArticleDOI

A Variation-aware Hold Time Fixing Methodology for Single Flux Quantum Logic Circuits

TL;DR: In this article, single flux quantum (SFQ) logic is proposed as a promising technology to replace complementary metal-oxide-semiconductor logic for future exa-scale supercomputing but requires the development of reliable EDA.
Proceedings ArticleDOI

Energy optimal sizing of FinFET standard cells operating in multiple voltage regimes using adaptive independent gate control

TL;DR: An effective design framework of FinFET standard cells based on the adaptive independent gate control method such that they can operate properly at all of subthreshold, near-th threshold and super-threshold regions is proposed.
Proceedings ArticleDOI

HIPE-MAGIC: a technology-aware synthesis and mapping flow for highly parallel execution of memristor-aided LoGIC

TL;DR: In this article, the authors present HIPE-MAGIC, a technology-aware synthesis and mapping flow for highly parallel execution of the memristor-based logic, which is built upon two fundamental contributions: balancing techniques during the logic synthesis, mainly targeting benefits of the parallelism offered by memristive crossbar arrays (MCAs), and an efficient technology mapping framework to maximize the performance and area-efficiency.

A f ast and e fficient c onditional l earning for t unable t rade - off between a ccuracy and r o bustness

TL;DR: In this paper , the authors proposed a novel weight conditioned adversarial training (FLOAT) algorithm, which requires no additional layer, thereby incurring no significant increase in parameter count, training time, or network latency compared to standard adversarial learning.
Book ChapterDOI

Post Mapping Structural Optimization for Low Power

TL;DR: In this book, the structural optimization techniques have recently been introduced as a new optimization step in logic synthesis.