M
Massoud Pedram
Researcher at University of Southern California
Publications - 812
Citations - 25236
Massoud Pedram is an academic researcher from University of Southern California. The author has contributed to research in topics: Energy consumption & CMOS. The author has an hindex of 77, co-authored 780 publications receiving 23047 citations. Previous affiliations of Massoud Pedram include University of California, Berkeley & Syracuse University.
Papers
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Proceedings ArticleDOI
An architecture-level approach for mitigating the impact of process variations on extensible processors
TL;DR: An architecture-level approach to mitigate the impact of process variations on extended instruction set architectures (ISAs) is presented and a new merit function for selecting the CIs during the selection phase of the ISA extension design flow is introduced.
Journal ArticleDOI
Statistical Functional Yield Estimation and Enhancement of CNFET-Based VLSI Circuits
TL;DR: It is shown that enhancing the CNT synthesis process alone cannot achieve acceptable functional yield for upcoming CNFET-based VLSI circuits, so a technique based on replacing each transistor by series-parallel transistor structures to reduce the failure probability of C NFETs in the presence of metallic and nonuniform CNTs is proposed.
Journal ArticleDOI
An 8-b Multiplier Using Single-Stage Full Adder Cell in Single-Flux-Quantum Circuit Technology
TL;DR: In this paper, a 1-b full adder with sum and carries as two individual single-stage FDQ gates is proposed, and both of the sum and carry cells are demonstrated with their schematics and layouts.
Proceedings ArticleDOI
Distributed multimedia system design: a holistic perspective
TL;DR: This paper addresses a few fundamental issues that make the design process particularly challenging and offers a holistic perspective towards a coherent design methodology.
Proceedings ArticleDOI
Platform-dependent, leakage-aware control of the driving current of embedded thermoelectric coolers
TL;DR: Experimental results show that, with this policy, one can reduce the temperature of chip hotspots while achieving a high COP, and a platform-dependent, leakage-aware cooling policy is proposed.