There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

Machine Learning is the study of methods for programming computers to learn. Computers are applied to a wide range of tasks, and for most of these it is relatively easy for programmers to design and implement the necessary software. However, there are many tasks for which this is difficult or impossible. These can be divided into four general categories. First, there are problems for which there exist no human experts. For example, in modern automated manufacturing facilities, there is a need to predict machine failures before they occur by analyzing sensor readings. Because the machines are new, there are no human experts who can be interviewed by a programmer to provide the knowledge necessary to build a computer system. A machine learning system can study recorded data and subsequent machine failures and learn prediction rules. Second, there are problems where human experts exist, but where they are unable to explain their expertise. This is the case in many perceptual tasks, such as speech recognition, hand-writing recognition, and natural language understanding. Virtually all humans exhibit expert-level abilities on these tasks, but none of them can describe the detailed steps that they follow as they perform them. Fortunately, humans can provide machines with examples of the inputs and correct outputs for these tasks, so machine learning algorithms can learn to map the inputs to the outputs. Third, there are problems where phenomena are changing rapidly. In finance, for example, people would like to predict the future behavior of the stock market, of consumer purchases, or of exchange rates. These behaviors change frequently, so that even if a programmer could construct a good predictive computer program, it would need to be rewritten frequently. A learning program can relieve the programmer of this burden by constantly modifying and tuning a set of learned prediction rules. Fourth, there are applications that need to be customized for each computer user separately. Consider, for example, a program to filter unwanted electronic mail messages. Different users will need different filters. It is unreasonable to expect each user to program his or her own rules, and it is infeasible to provide every user with a software engineer to keep the rules up-to-date. A machine learning system can learn which mail messages the user rejects and maintain the filtering rules automatically. Machine learning addresses many of the same research questions as the fields of statistics, data mining, and psychology, but with differences of emphasis. Statistics focuses on understanding the phenomena that have generated the data, often with the goal of testing different hypotheses about those phenomena. Data mining seeks to find patterns in the data that are understandable by people. Psychological studies of human learning aspire to understand the mechanisms underlying the various learning behaviors exhibited by people (concept learning, skill acquisition, strategy change, etc.).

Machine learning

Probability Distributions.- Linear Models for Regression.- Linear Models for Classification.- Neural Networks.- Kernel Methods.- Sparse Kernel Machines.- Graphical Models.- Mixture Models and EM.- Approximate Inference.- Sampling Methods.- Continuous Latent Variables.- Sequential Data.- Combining Models.

Pattern Recognition and Machine Learning

/pdf/convex-analysisnoer-san-nojin-zhan-nituite-5dl2rbmoyr.pdf

Convex Analysisの二,三の進展について

The Multi-Threshold CMOS (MTCMOS) technique can significantly reduce sub-threshold leakage currents during the circuit sleep (standby) mode by adding high-V/sub th/ power switches (sleep transistors) to low-V/sub th/ logic cells. During the active mode of the circuit, the high-V/sub th/ transistors and the virtual ground network can be modeled as resistors, which in turn cause voltage of the virtual ground node to rise thereby degrading the switching speed of the logic cells. This paper introduces a new design methodology that minimizes the impact of virtual ground parasitic resistances on the performance of an MTCMOS circuit by using gate resizing and logic restructuring (i.e., gate replication.) Experimental results show that the proposed techniques are highly effective in making the MTCMOS circuits robust with respect to such parasitic resistance effects.

Gate Sizing and Replication to Minimize the Effects of Virtual Ground Parasitic Resistances in MTCMOS Designs

As IC fabrication capabilities extend down to sub-halfmicron, the signi cance of interconnect delay and power dissipation can no longer be ignored. Existing enhancements to synthesis and physical design tools (such as nonlinear delay modeling, custom wire load models, back annotation of calculated delays, early oorplanning, post-layout re-mapping and resizing) have not been able to solve the problem. It thus remains that tradeo s in logical and physical domains must be addressed in an integrated fashion. Huge business opportunities will be lost unless more revolutionary changes to design ow are made. This panel of experts will address the current split between logic synthesis and physical design and its e ect on the design ow. It will then discuss possibilities for merging the two, or at least bringing them closer together. In particular, issues such as consistent wire load and timing models and algorithms which must be employed across the design ow, EDA standards and common databases to support the integration of layout and synthesis tools, evolving structured design styles that o er lower wiring overhead, interconnect-driven logic synthesis, and timingdriven physical design will be discussed. Finally, the panel will seek to highlight challenges and potential pitfalls that lie ahead.

/pdf/panel-physical-design-and-synthesis-merge-or-die-5c9ec00k5p.pdf

Panel: Physical Design And Synthesis: Merge Or Die

Hierarchical power management of a system with autonomously power-managed components using reinforcement learning

This paper presents an exact algorithm and two heuristics for solving the Bounded path length Minimal Spanning Tree (BMST) problem. The exact algorithm which is based on iterative negative-sum-exchange(s) has polynomial space complexity and is hence more practical than the method presented by Gabow. The first heuristic method (BKRUS) is based on the classical Kruskal MST construction. For any given value of parameter /spl epsiv/, the algorithm constructs a routing tree with the longest interconnection path length at most (1+/spl epsiv/).R, and empirically with cost at most 1.19 times cost (BMST*) where R is the length of the direct path from the source to the farthest sink and BMST* is the optimal bounded path length MST. The second heuristic combines BKRUS and negative-sum-exchange(s) of depth 2 to improve results. Extensions of these techniques to the bounded path length Minimal Steiner Trees, using the Elmore delay model are presented as well. Empirical results demonstrate the effectiveness of these algorithms on a large benchmark set.

/pdf/constructing-minimal-spanning-steiner-trees-with-bounded-3sfyvjua85.pdf

Constructing minimal spanning/Steiner trees with bounded path length

A method of forming a memory cell includes coupling a first transistor between a supply rail of a memory cell and a node operable to accept a supply voltage. The method further includes coupling a second transistor between a ground rail of the cell and a node operable to accept a ground. In one embodiment, the method includes forming the cell to accept selectively applied external voltages, wherein the external voltages are selected to minimize leakage current in the cell. In another embodiment, the method includes forming at least one of the first and the second transistors to have a channel width and/or a threshold voltage selected to minimize a total leakage current in the cell.

Massoud Pedram

Papers

Gate Sizing and Replication to Minimize the Effects of Virtual Ground Parasitic Resistances in MTCMOS Designs

Panel: Physical Design And Synthesis: Merge Or Die

Hierarchical power management of a system with autonomously power-managed components using reinforcement learning

Constructing minimal spanning/Steiner trees with bounded path length

PG-gated data retention technique for reducing leakage in memory cells