M
Massoud Pedram
Researcher at University of Southern California
Publications - 812
Citations - 25236
Massoud Pedram is an academic researcher from University of Southern California. The author has contributed to research in topics: Energy consumption & CMOS. The author has an hindex of 77, co-authored 780 publications receiving 23047 citations. Previous affiliations of Massoud Pedram include University of California, Berkeley & Syracuse University.
Papers
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Journal ArticleDOI
A comparative study on performance and reliability of 32-bit binary adders
TL;DR: The performance and reliability of different binary adder families are studied for both the superthreshold and the near-threshold regions of operation and the reliability parameters are a function of the adder architectures.
Proceedings ArticleDOI
Simultaneous gate sizing and fanout optimization
TL;DR: An algorithm for simultaneous gate sizing and fanout optimization along the timing-critical paths in a circuit is described and a design flow based on iterative selection and optimization of the k most critical paths in the circuit is proposed.
Proceedings ArticleDOI
Challenges and the status of superconducting single flux quantum technology
TL;DR: This paper starts by describing key differences between SFQ logic and conventional CMOS and concludes by listing key challenges that must be overcome to achieve the very large scale integration of SFQ circuits and make the demonstration of a superconductive CPU a reality.
Journal ArticleDOI
DART: A Framework for Determining Approximation Levels in an Approximable Memory Hierarchy
TL;DR: A framework for determining approximation levels of approximable memories in a memory hierarchy for executing error resilient applications and compares energy consumptions of approximate memories with those of the exact memory units in the memory hierarchy under different output accuracy level targets is proposed.
Proceedings ArticleDOI
Minimizing the energy-delay product of SRAM arrays using a device-circuit-architecture co-optimization framework
TL;DR: At the device-level, high-Vt FinFETs are adopted for the 6T SRAM cell, which significantly reduces the leakage power and improves static noise margins, but due to the lower ON current, the bitline delay of the read access is increased.