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Massoud Pedram

Researcher at University of Southern California

Publications -  812
Citations -  25236

Massoud Pedram is an academic researcher from University of Southern California. The author has contributed to research in topics: Energy consumption & CMOS. The author has an hindex of 77, co-authored 780 publications receiving 23047 citations. Previous affiliations of Massoud Pedram include University of California, Berkeley & Syracuse University.

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Journal ArticleDOI

Concurrent Task Scheduling and Dynamic Voltage and Frequency Scaling in a Real-Time Embedded System With Energy Harvesting

TL;DR: This paper proposes a cascaded feedback control structure, where an outer supervisory control loop performs real-time task scheduling with DVFS in the sensor node while maintaining the optimal supercapacitor SoC for improved system availability.
Proceedings ArticleDOI

LEOPARD: a Logical Effort-based fanout OPtimizer for ARea and Delay

TL;DR: LEOPARD is a fanout optimization algorithm based on the effort delay model for near-continuous size buffer libraries that minimizes area under required timing and input capacitance constraints by finding the tree topology and assigning different gains to each buffer to minimize the total buffer area.
Proceedings ArticleDOI

Post-layout timing-driven cell placement using an accurate net length model with movable Steiner points

TL;DR: A new algorithm for timing-driven cell placement using the notion of movable Steiner points that capture the net topology is presented, which improves the timing closure at the backend of the EDA design flow.
Journal ArticleDOI

Frame-Based Dynamic Voltage and Frequency Scaling for an MPEG Player

TL;DR: A dynamic voltage and frequency scaling (DVFS) technique for MPEG decoding to reduce the energy consumption while maintaining a quality of service (QoS) constraint is described and two key benefits depending on the hardware platform are provided.
Proceedings ArticleDOI

I/O pad assignment based on the circuit structure

TL;DR: Experimental data show that as a result of using the I/O pad assignment procedure, the total interconnection length and circuit delay are reduced by 8-15% and 3-4%, respectively.