M
Massoud Pedram
Researcher at University of Southern California
Publications - 812
Citations - 25236
Massoud Pedram is an academic researcher from University of Southern California. The author has contributed to research in topics: Energy consumption & CMOS. The author has an hindex of 77, co-authored 780 publications receiving 23047 citations. Previous affiliations of Massoud Pedram include University of California, Berkeley & Syracuse University.
Papers
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Journal ArticleDOI
Fast Interconnect and Gate Timing Analysis for Performance Optimization
TL;DR: This paper presents sufficiently accurate and highly efficient filtering algorithms for interconnect timing as well as gate timing analysis, and shows accuracies that are quite comparable with sign-off delay calculators with more than of 65% reduction in the computation times.
Proceedings ArticleDOI
SACI: statistical static timing analysis of coupled interconnects
TL;DR: A new framework for handling the effect of Gaussian and Non-Gaussian process variations on coupled interconnects is proposed and Experimental results show that the proposed method is capable of accurately predicting delay variation in a coupled interConnect line.
Journal ArticleDOI
CSAM: A clock skew-aware aging mitigation technique
B. Eghbalkhah,Mehdi Kamal,Ali Afzali-Kusha,Mohammad Bagher Ghaznavi-Ghoushchi,Massoud Pedram +4 more
TL;DR: A clock skew-aware aging mitigation technique which considers the effect of asymmetric aging both on logic path and clock tree together and simultaneous consideration of both parts in the design optimization problem enables us to reduce the area overhead while increasing the lifetime.
Proceedings ArticleDOI
An energy-aware simulation model and transaction protocol for dynamic workload distribution in mobile ad hoc networks
TL;DR: An energy-aware network transaction protocol is presented that dynamically redistributes the computational workload among a set of cooperative hosts within a MANET so as to improve network performance (network lifetime and service latency).
Proceedings ArticleDOI
Characterization and design of sequential circuit elements to combat soft error
TL;DR: This paper performs analysis and design of latches and flip-flops while considering the effect of event upsets caused by energetic particle hits, and explains how to size transistors of a familiar SCE i.e., a clocked CMOS latch to make it more robust to such events.