There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

Machine Learning is the study of methods for programming computers to learn. Computers are applied to a wide range of tasks, and for most of these it is relatively easy for programmers to design and implement the necessary software. However, there are many tasks for which this is difficult or impossible. These can be divided into four general categories. First, there are problems for which there exist no human experts. For example, in modern automated manufacturing facilities, there is a need to predict machine failures before they occur by analyzing sensor readings. Because the machines are new, there are no human experts who can be interviewed by a programmer to provide the knowledge necessary to build a computer system. A machine learning system can study recorded data and subsequent machine failures and learn prediction rules. Second, there are problems where human experts exist, but where they are unable to explain their expertise. This is the case in many perceptual tasks, such as speech recognition, hand-writing recognition, and natural language understanding. Virtually all humans exhibit expert-level abilities on these tasks, but none of them can describe the detailed steps that they follow as they perform them. Fortunately, humans can provide machines with examples of the inputs and correct outputs for these tasks, so machine learning algorithms can learn to map the inputs to the outputs. Third, there are problems where phenomena are changing rapidly. In finance, for example, people would like to predict the future behavior of the stock market, of consumer purchases, or of exchange rates. These behaviors change frequently, so that even if a programmer could construct a good predictive computer program, it would need to be rewritten frequently. A learning program can relieve the programmer of this burden by constantly modifying and tuning a set of learned prediction rules. Fourth, there are applications that need to be customized for each computer user separately. Consider, for example, a program to filter unwanted electronic mail messages. Different users will need different filters. It is unreasonable to expect each user to program his or her own rules, and it is infeasible to provide every user with a software engineer to keep the rules up-to-date. A machine learning system can learn which mail messages the user rejects and maintain the filtering rules automatically. Machine learning addresses many of the same research questions as the fields of statistics, data mining, and psychology, but with differences of emphasis. Statistics focuses on understanding the phenomena that have generated the data, often with the goal of testing different hypotheses about those phenomena. Data mining seeks to find patterns in the data that are understandable by people. Psychological studies of human learning aspire to understand the mechanisms underlying the various learning behaviors exhibited by people (concept learning, skill acquisition, strategy change, etc.).

Machine learning

Probability Distributions.- Linear Models for Regression.- Linear Models for Classification.- Neural Networks.- Kernel Methods.- Sparse Kernel Machines.- Graphical Models.- Mixture Models and EM.- Approximate Inference.- Sampling Methods.- Continuous Latent Variables.- Sequential Data.- Combining Models.

Pattern Recognition and Machine Learning

/pdf/convex-analysisnoer-san-nojin-zhan-nituite-5dl2rbmoyr.pdf

Convex Analysisの二,三の進展について

With the emergence of large-scale single-flux-quantum (SFQ) circuits, it is desirable to offload heavy routing tasks to automated electronic design automation (EDA) tools. The unique characteristic of SFQ circuits is that large clock distribution networks are generally required to pass the clock signal to clocked cells subject to limited fanout drive capability of the intervening clock buffers. This scenario results in a huge challenge to control the clock skew and minimize the signal path delays in an SFQ circuit during the routing step. Values of the clock skew and path delays determine not only the maximum working frequencies but also whether or not there are hold time violations. However, it is not necessary to develop a timing-driven routing tool specifically for SFQ circuits from scratch because the number of the paths that set the maximum clock frequencies or give rise to hold time violations is generally very small. Thus, we present a novel postrouting optimization framework that augments standard maze routing tools by adding the capability of reducing path lengths to maximize the working frequency of the chip and meandering paths to avoid hold time violations. A framework is developed in which machine learning is applied to analyze wire distributions and a maze routing algorithm is used to reroute targeted paths. Based on the MIT-LL SFQ5ee process technology, we demonstrate that our framework can improve the minimum working frequency by 7$\\%$ on average over the state-of-the-art EDA routing tool for a suite of 14 SFQ circuits while fixing all hold time violations.

Postrouting Optimization of the Working Clock Frequency of Single-Flux-Quantum Circuits

1 A preliminary version of this work has appeared in Proceedings of ASP-DAC 2003. ABSTRACT Leakage power and hot-carrier effects are emerging as key concerns in deep sub-micron CMOS technologies with respect to their effects on the total power dissipation and reliability of VLSI circuits. Leakage power dissipation is rapidly becoming a substantial contributor to the total power dissipation as threshold voltage becomes small. Similarly, the hot-carrier effect is one of the most significant failure mechanisms in high-density VLSI circuits. In this paper, a technology mapping technique is presented for use in reducing the leakage power dissipation of the circuit by utilizing a dual-threshold voltage cell library and for minimizing the aged delay of the circuit by considering the effect of hot carriers on the cell speeds as the circuit ages. In addition, this paper presents two methods to reduce delay during technology mapping: primary output ordering and pin permutation. Experimental results show that the total power dissipation and leakage power dissipation can be reduced by up to 27% and 52% as a result of the leakage-aware technology mapping and that the circuit aging phenomenon can be reduced by up to 10.6% as a result of hot-carrier-aware technology mapping. Delay was also reduced by up to 13% using primary output ordering and pin permutation.

A Leakage-Aware Low Power Technology Mapping Algorithm Considering the Hot-Carrier Effect

This paper presents a novel architectural mechanism and a power management structure for the design of an energy-efficient gigabit Ethernet controller. Key characteristics of such a controller are low-latency and high-bandwidth required to meet the pressing demands of extremely high frame and control data, which in turn cause difficulties in managing power dissipation. We propose a flow-through-queue (FTQ) based power management method, which allows some of the tasks involved in processing the frame data to be offloaded. This in turn enables utilization of multiple clock rates and multiple voltages for different cores inside the Ethernet controller. A modeling approach based on semi-Markov decision process (SMDP) and queuing models is employed, which allow one to apply mathematical programming formulations for energy optimization under performance constraints. The proposed gigabit Ethernet controller is designed with a 130nm CMOS technology that includes both high and low threshold voltages. Experimental results show that the proposed power optimization method can achieve system-wide energy savings under tighter performance constraints.

http://www.cecs.uci.edu/~papers/aspdac07/pdf/p571_6B-1.pdf

Flow-Through-Queue based Power Management for Gigabit Ethernet Controller

Retiming, which is a circuit transformation whereby registers are relocated to optimize performance, area, or energy consumption, has reached a high level of maturity in CMOS designs. However, the recent emergence and rapid rise of non-CMOS technologies are introducing new and important variants of the standard retiming problems. This paper presents a path-balancing retiming transformation, taking superconductive designs as an evaluation case study, where the retiming solution must achieve full path balancing of the circuit while simultaneously minimizing the energy consumption of inserted registers with performance constraints. This optimization problem, which is called a constrained register energy minimization (CREM) problem, is precisely formulated and polynomially solved. Next, the CREM problem formulation is extended to retime the circuit under a dual clocking architecture requiring partially (bounded depth difference) path balanced (PPB) characteristics only. It is shown that the PPB-CREM problem is NP-complete. We thus propose a polynomial-time approximation algorithm with a bounded error to solve this retiming variant. Compared to prior work, our approach reduces 38% of register count and 50% of register energy consumption of 14 benchmark circuits on average. Moreover, the competitive ratio of the register energy consumption between our approximate solution and the optimal solution is on average only 1.08.

https://dl.acm.org/doi/pdf/10.1145/3400302.3415659

Retiming for high-performance superconductive circuits with register energy minimization

PV module reconfiguration techniques have been proposed to combat the partial shading effect. These techniques can adaptively change the PV module configuration according to the partial shading pattern. A reconfigurable PV module is designed by integrating three programmable switches with each PV macro-cell. The PV module reconfiguration is then realized by controlling the ON/OFF states of the switches. To reduce the additional capital cost induced by the switches, we propose to optimize the switch configurations, i.e., derive the required number of MOSFETs in each switch based on the maximum current passing through that switch, in a reconfigurable PV module. The optimal switch configuration design combined with the optimization of PV macro-cell size can make the reconfigurable PV module achieve the maximum performance enhancement under partial shading while satisfying the capital cost constraint of the PV module.

Massoud Pedram

Papers

Postrouting Optimization of the Working Clock Frequency of Single-Flux-Quantum Circuits

A Leakage-Aware Low Power Technology Mapping Algorithm Considering the Hot-Carrier Effect

Flow-Through-Queue based Power Management for Gigabit Ethernet Controller

Retiming for high-performance superconductive circuits with register energy minimization

Optimal switch configuration design for reconfigurable photovoltaic modules