M
Matteo Sonza Reorda
Researcher at Polytechnic University of Turin
Publications - 340
Citations - 5043
Matteo Sonza Reorda is an academic researcher from Polytechnic University of Turin. The author has contributed to research in topics: Fault coverage & Automatic test pattern generation. The author has an hindex of 32, co-authored 295 publications receiving 4525 citations. Previous affiliations of Matteo Sonza Reorda include University of California, Riverside & NXP Semiconductors.
Papers
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Proceedings ArticleDOI
Reliability analysis reloaded: how will we survive?
Robert Campbell Aitken,Görschwin Fey,Zbigniew Kalbarczyk,Frank Reichenbach,Matteo Sonza Reorda +4 more
TL;DR: This paper revisits the state-of-the-art in reliability evaluation starting from the physical device level, to the software system level, all the way up to the product level.
Book ChapterDOI
Software-level soft-error mitigation techniques
TL;DR: This chapter provides an overview of the methods resorting to Soft Errors, outlining their characteristics and summarizing their advantages and limitations.
Proceedings ArticleDOI
Effectiveness and limitations of various software techniques for "soft error" detection: a comparative study
TL;DR: Fault injection experiments put in evidence the detection capabilities and the limitations of each of the studied techniques for bit flip errors arising in microprocessor-based digital architectures as the consequence of the interaction with radiation.
Journal ArticleDOI
Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits
Maksim Jenihhin,Giovanni Squillero,Thiago Santos Copetti,Valentin Tihhomirov,Sergei Kostin,Marco Gaudesi,Fabian Vargas,Jaan Raik,Matteo Sonza Reorda,Leticia Bolzani Poehls,Raimund Ubar,Guilherme Cardoso Medeiros +11 more
TL;DR: A new, fast, yet accurate model for computation of NBTI-induced delays at gate-level is developed, based on intensive SPICE simulations of individual gates and the generated rejuvenation stimuli are used to drive those pMOS transistors to the recovery phase, which are the most critical for the NBTi-induced path delay.
Proceedings ArticleDOI
A genetic algorithm for automatic generation of test logic for digital circuits
TL;DR: This approach is the first attempt of exploiting evolutionary techniques for identifying the hardware for input pattern generation in BIST structures and shows that in most of the standard benchmark circuits the cellular automaton selected by the genetic algorithm is able to reach a fault coverage close to the maximum one.