: This research organizes, presents, and analyzes contemporary Multiobjective Evolutionary Algorithm (MOEA) research and associated Multiobjective Optimization Problems (MOPs). Using a consistent MOEA terminology and notation, each cited MOEAs' key factors are presented in tabular form for ease of MOEA identification and selection. A detailed quantitative and qualitative MOEA analysis is presented, providing a basis for conclusions about various MOEA-related issues. The traditional notion of building blocks is extended to the MOP domain in an effort to develop more effective and efficient MOEAs. Additionally, the MOEA community's limited test suites contain various functions whose origins and rationale for use are often unknown. Thus, using general test suite guidelines appropriate MOEA test function suites are substantiated and generated. An experimental methodology incorporating a solution database and appropriate metrics is offered as a proposed evaluation framework allowing absolute comparisons of specific MOEA approaches. Taken together, this document's classifications, analyses, and new innovations present a complete, contemporary view of current MOEA "state of the art" and possible future research. Researchers with basic EA knowledge may also use part of it as a largely self-contained introduction to MOEAs.

Multiobjective evolutionary algorithms: classifications, analyses, and new innovations

From the Publisher:
This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.

Algorithms for VLSI Physical Design Automation

This paper is the result of a literature study carried out by the authors. It is a review of the different attempts made to solve the Travelling Salesman Problem with Genetic Algorithms. We present crossover and mutation operators, developed to tackle the Travelling Salesman Problem with Genetic Algorithms with different representations such as: binary representation, path representation, adjacency representation, ordinal representation and matrix representation. Likewise, we show the experimental results obtained with different standard examples using combination of crossover and mutation operators in relation with path representation.

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Genetic Algorithms for the Travelling Salesman Problem: A Review of Representations and Operators

Hybrid metaheuristics have received considerable interest these recent years in the field of combinatorial optimization. A wide variety of hybrid approaches have been proposed in the literature. In this paper, a taxonomy of hybrid metaheuristics is presented in an attempt to provide a common terminology and classification mechanisms. The taxonomy, while presented in terms of metaheuristics, is also applicable to most types of heuristics and exact optimization algorithms.

As an illustration of the usefulness of the taxonomy an annoted bibliography is given which classifies a large number of hybrid approaches according to the taxonomy.

A Taxonomy of Hybrid Metaheuristics

We consider a fully SAT-based method of unbounded symbolic model checking based on computing Craig interpolants. In benchmark studies using a set of large industrial circuit verification instances, this method is greatly more efficient than BDD-based symbolic model checking, and compares favorably to some recent SAT-based model checking methods on positive instances.

Interpolation and SAT-based model checking

A Cellular Genetic Algorithm for the Floorplan Area Optimization Problem on a SIMD Architecture

Politecnico di Torino has been actively experimenting distance education scenarios since 1992, through the development of innovative methodologies and tools. The real challenge today, however, is to move from small settings to a large-scale system able to suit the needs of a broad number of users belonging to different categories, from traditional students to part-time or full-time workers, from students living far from Torino to people with participation restriction due to disability. The emphasis then, is not only on the innovation of methodologies and technologies, but on their effective and economically sustain- able use in a complex and multi-faceted setting. This chapter describes the services introduced in this direction and gives a preliminary evaluation after the first year of delivery

E-Learning at Politecnico di Torino: Moving to a Sustainable Large-Scale Multi-Channel System of Services

Automotive System-on-Chip (SoC) performances have enormously increased in the last decade. Therefore, bare-metal safety-critical applications have shifted to the new application paradigm written at the Operating System layer, i.e., on top of Real-Time Operating Systems (RTOS). The RTOS stores needed data and instructions in the embedded memories. Therefore, potential corruption in these memories could generate non-deterministic, wrong behaviors. Online software or hardware testing mechanisms detect and sometimes correct such dangerous situations. In either case, the application programmer has to devise special tasks devoted to testing and must ensure fully working synchronization mechanisms without impacting the feasibility of the RTOS scheduler. This paper investigates the impact on the scheduling and reliability of an RTOS when hardware and software memory BIST periodically test embedded RAMs in the field. The results are obtained on a real automotive SoC belonging to the SPC58 family from ST Microelectronics.

Online scheduling of concurrent Memory BISTs execution at Real-Time Operating-System level

Digital integrated circuits require thorough testing in order to guarantee product quality. This is usually achieved with the use of scan chains and automatically generated test patterns. However, functional approaches are often used to complement test suites. Software-Based Self-Test (SBST) can be used to increase defect coverage in microcontrollers, to replace part of the scan pattern set to reduce tester requirements, or to complement the defect coverage achieved by structural techniques when advanced semiconductor technologies introduce new defect types. Delay testing has become common practice with VLSI integration, and with the latest technologies, targeting small delay defects (SDDs) has become necessary. This chapter deals with SBST for delay faults and describes a case of study based on a peripheral module integrated in a System on Chip (SoC). A method to develop an effective functional test is first described. A comparative analysis of the delay faults detected by scan and SBST is then presented, with some discussion about the obtained results.

Software-Based Self-Test for Delay Faults

Software-Based Self-Test (SBST) approaches have shown to be an effective solution to detect permanent faults, both at the end of the production process, and during the operational phase. However, when Very Long Instruction Word (VLIW) processors are addressed these techniques require some optimization steps in order to properly exploit the parallelism intrinsic in these architectures. In this chapter we present a new method that, starting from previously known algorithms, automatically generates an effective test program able to still reach high fault coverage on the VLIW processor under test, while minimizing the test duration and the test code size. Moreover, using this method, a set of small SBST programs can be generated aimed at the diagnosis of the VLIW processor. Experimental results gathered on a case study show the effectiveness of the proposed approach.

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Matteo Sonza Reorda

Papers

A Cellular Genetic Algorithm for the Floorplan Area Optimization Problem on a SIMD Architecture

E-Learning at Politecnico di Torino: Moving to a Sustainable Large-Scale Multi-Channel System of Services

Online scheduling of concurrent Memory BISTs execution at Real-Time Operating-System level

Software-Based Self-Test for Delay Faults

On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors