: This research organizes, presents, and analyzes contemporary Multiobjective Evolutionary Algorithm (MOEA) research and associated Multiobjective Optimization Problems (MOPs). Using a consistent MOEA terminology and notation, each cited MOEAs' key factors are presented in tabular form for ease of MOEA identification and selection. A detailed quantitative and qualitative MOEA analysis is presented, providing a basis for conclusions about various MOEA-related issues. The traditional notion of building blocks is extended to the MOP domain in an effort to develop more effective and efficient MOEAs. Additionally, the MOEA community's limited test suites contain various functions whose origins and rationale for use are often unknown. Thus, using general test suite guidelines appropriate MOEA test function suites are substantiated and generated. An experimental methodology incorporating a solution database and appropriate metrics is offered as a proposed evaluation framework allowing absolute comparisons of specific MOEA approaches. Taken together, this document's classifications, analyses, and new innovations present a complete, contemporary view of current MOEA "state of the art" and possible future research. Researchers with basic EA knowledge may also use part of it as a largely self-contained introduction to MOEAs.

Multiobjective evolutionary algorithms: classifications, analyses, and new innovations

From the Publisher:
This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.

Algorithms for VLSI Physical Design Automation

This paper is the result of a literature study carried out by the authors. It is a review of the different attempts made to solve the Travelling Salesman Problem with Genetic Algorithms. We present crossover and mutation operators, developed to tackle the Travelling Salesman Problem with Genetic Algorithms with different representations such as: binary representation, path representation, adjacency representation, ordinal representation and matrix representation. Likewise, we show the experimental results obtained with different standard examples using combination of crossover and mutation operators in relation with path representation.

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Genetic Algorithms for the Travelling Salesman Problem: A Review of Representations and Operators

Hybrid metaheuristics have received considerable interest these recent years in the field of combinatorial optimization. A wide variety of hybrid approaches have been proposed in the literature. In this paper, a taxonomy of hybrid metaheuristics is presented in an attempt to provide a common terminology and classification mechanisms. The taxonomy, while presented in terms of metaheuristics, is also applicable to most types of heuristics and exact optimization algorithms.

As an illustration of the usefulness of the taxonomy an annoted bibliography is given which classifies a large number of hybrid approaches according to the taxonomy.

A Taxonomy of Hybrid Metaheuristics

We consider a fully SAT-based method of unbounded symbolic model checking based on computing Craig interpolants. In benchmark studies using a set of large industrial circuit verification instances, this method is greatly more efficient than BDD-based symbolic model checking, and compares favorably to some recent SAT-based model checking methods on positive instances.

Interpolation and SAT-based model checking

In this paper we describe how we applied a BIST-based approach to the test of a logic core to be included in System-on-a-chip (SoC) environments. The approach advantages are the ability to protect the core IP, the simple test interface (thanks also to the adoption of the P1500 standard), the possibility to run the test at-speed, the reduced test time, and the good diagnostic capabilities. The paper reports figures about the achieved fault coverage, the required area overhead, and the performance slowdown, and compares the figures with those for alternative approaches, such as those based on full scan and sequential ATPG.

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Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study

System-level test, or SLT, is an increasingly important process step in today's integrated circuit testing flows. Broadly speaking, SLT aims at executing functional workloads in operational modes. In this paper, we consolidate available knowledge about what SLT is precisely and why it is used despite its considerable costs and complexities. We discuss the types or failures covered by SLT, and outline approaches to quality assessment, test generation and root-cause diagnosis in the context of SLT. Observing that the theoretical understanding for all these questions has not yet reached the level of maturity of the more conventional structural and functional test methods, we outline new and promising directions for methodical developments leveraging on recent findings from software engineering.

Exploring the Mysteries of System-Level Test

Modern devices often include several embedded instruments, such as BISTs, sensors, and other analogcomponents. New standards, such as IEEE Std. 1687, providevehicles to access these instruments. In approaches based onreconfigurable scan networks, instruments are coupled withscan registers, connected into chains and interleaved withreconfigurable multiplexers, permitting a selective access todifferent parts of the chain. A similar scenario is also supportedby IEEE Std. 1149.1-2013, where a test data register can beconstructed as a chain of multiple segments, some of which canbe excluded or mutually selected. The test of permanent faultsaffecting a reconfigurable scan network requires to shift testpatterns throughout a certain number of network configurations. This paper presents a method to select the list of configurationsneeded to apply the complete test set in the minimum amount ofclock cycles. The method is based on a graph representation ofthe problem. Experimental results on some benchmark networksare provided, together with a comparison with other approachesbased on heuristics. The provided results can be effectively usedto evaluate the test time of sub-optimal approaches.

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Test Time Minimization in Reconfigurable Scan Networks

With the adoption of deep sub-micron technologies, faults modeled as single event transients (SETS) on combinational gates are becoming an issue, but efficient and accurate techniques for assessing their impact on VLSI designs are still missing. This paper presents a new approach for generating the list of faults to be addressed during fault injection experiments tackling SET effects. By resorting to static timing analysis, the approach is able to prune the set of possible faults and to identify a superset of the ones that may produce effects on the circuit outputs. Experimental results are reported on standard benchmarks assessing the effectiveness of the proposed approach.

Fault list compaction through static timing analysis for efficient fault injection experiments

Designers of safety-critical VLSI systems are asking for effective tools for evaluating and validating their designs Fault Injection is commonly adopted for this task, and its effectiveness is therefore a key factor In this paper we propose to exploit FPGAs to speed-up Fault Injection for fault tolerance evaluation of VLSI circuits A complete Fault Injection environment is described, relying on FPGA-based emulation of the circuit for fault effect analysis The proposed approach allows combining the efficiency of hardware-based techniques, and the flexibility of simulation-based techniques Experimental results are provided to support the feasibility and effectiveness of the approach

Matteo Sonza Reorda

Papers

Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study

Exploring the Mysteries of System-Level Test

Test Time Minimization in Reconfigurable Scan Networks

Fault list compaction through static timing analysis for efficient fault injection experiments

FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits