M
Matteo Sonza Reorda
Researcher at Polytechnic University of Turin
Publications - 340
Citations - 5043
Matteo Sonza Reorda is an academic researcher from Polytechnic University of Turin. The author has contributed to research in topics: Fault coverage & Automatic test pattern generation. The author has an hindex of 32, co-authored 295 publications receiving 4525 citations. Previous affiliations of Matteo Sonza Reorda include University of California, Riverside & NXP Semiconductors.
Papers
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Book ChapterDOI
Fault-Tolerance Techniques for Soft-Core Processors Using the Trace Interface
Luis Entrena,Almudena Lindoso,Marta Portela-Garcia,Luis Parra,Boyang Du,Matteo Sonza Reorda,Luca Sterpone +6 more
TL;DR: This paper focuses on the use of the trace interface for on-line monitoring that provides detailed information about the instructions executed by the processor and can be reused to support error detection and correction in several ways, including multi-processors in hardware redundancy, time redundancy and control-flow checking.
Journal ArticleDOI
Automatic test generation for verifying microprocessors
TL;DR: A pipelined processor with a high-level behavioral HDL description that generates a set of effective test programs by using a simulator, which is able to evaluate with respect to an RTL coverage metric is presented.
Journal ArticleDOI
An Effective Method to Identify Microarchitectural Vulnerabilities in GPUs
Josie E. Rodriguez Condia,Paolo Rech,Fernando Fernandes dos Santos,Luigi Carro,Matteo Sonza Reorda +4 more
TL;DR: This work proposes an effective methodology to identify the architectural vulnerable sites in GPUs modules, i.e., the locations that, if corrupted, most affect the correct instructions execution, and mitigate the fault impact via selective hardening applied to the flip-flops that have been identified as critical.
Journal ArticleDOI
Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption
Paolo Bernardi,Mauricio de Carvalho,Ernesto Sanchez,Matteo Sonza Reorda,Alberto Bosio,Luigi Dilillo,Miroslav Valka,Patrick Girard +7 more
TL;DR: A methodology combining neural networks and evolutionary computing for quickly estimating peak power consumption is presented, which was applied on the Intel 8051 CPU core synthesized with a 65 nm industrial technology reducing significant time with respect to old methods.