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Nidhi Nidhi
Researcher at Intel
Publications - 19
Citations - 442
Nidhi Nidhi is an academic researcher from Intel. The author has contributed to research in topics: Transistor & Gate dielectric. The author has an hindex of 6, co-authored 19 publications receiving 404 citations.
Papers
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Proceedings ArticleDOI
A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications
Chia-Hong Jan,Uddalak Bhattacharya,Ruth A. Brain,S.-J. Choi,G. Curello,G. Gupta,Hafez Walid M,M. Jang,M. Kang,K. Komeyli,T. Leo,Nidhi Nidhi,L. Pan,Joodong Park,Kinyip Phoa,Abdur Rahman,C. Staus,H. Tashiro,Curtis Tsai,P. Vandervoorn,L. Yang,J.-Y. Yeh,P. Bai +22 more
TL;DR: In this paper, a leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time, and a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages.
Proceedings ArticleDOI
A 14 nm SoC platform technology featuring 2 nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um 2 SRAM cells, optimized for low power, high performance and high density SoC products
C.-H. Jan,F. Al-Amoody,Chang Hsu-Yu,Tsung-Yuan Chang,Y.-W. Chen,N. L. Dias,Hafez Walid M,D. Ingerly,M. Jang,Eric Karl,S. K.-Y. Shi,K. Komeyli,H. Kilambi,A. Kumar,K. Byon,Chen-Guan Lee,J. Lee,T. Leo,Pei-Chi Liu,Nidhi Nidhi,Olac-Vaw Roman W,C. Petersburg,K. Phoa,Chetan Prasad,C. Quincy,Ramaswamy Rahul,T. Rana,L. Rockford,Anand Subramaniam,Curtis Tsai,P. Vandervoorn,L. Yang,A. Zainuddin,P. Bai +33 more
TL;DR: A leading edge 14 nm SoC platform technology based upon the 2nd generation Tri-Gate transistor technology has been optimized for density, low power and wide dynamic range and a full suite of analog, mixed-signal and RF features are supported.
Proceedings ArticleDOI
3D heterogeneous integration of high performance high-K metal gate GaN NMOS and Si PMOS transistors on 300mm high-resistivity Si substrate for energy-efficient and compact power delivery, RF (5G and beyond) and SoC applications
Han Wui Then,Huang Cheng-Ying,B. Krist,Kimin Jun,Kevin Lin,Nidhi Nidhi,T. Michaelos,Mueller Brennen,Rajat Kanti Paul,J. Peck,W. Rachmady,Sansaptak Dasgupta,D. Staines,T. Talukdar,Nicole K. Thomas,Tronic Tristan A,Fischer Paul B,Hafez Walid M,Marko Radosavljevic,P. Agababov,Ibrahim Ban,Robert L. Bristol,Manish Chandhok,Chouksey Siddharth,Brandon Holybee +24 more
TL;DR: In this paper, the authors have demonstrated industry's first 300mm 3D heterogeneous integration of high performance, low-leakage high-K dielectric e-mode GaN NMOS and Si PMOS transistors on 300mm high-resistivity (HR) Si(111) substrate, enabled by 300mm GaN MOCVD epitaxy and 3D layer transfer.
Proceedings ArticleDOI
Transistor reliability characterization and comparisons for a 14 nm tri-gate technology optimized for System-on-Chip and foundry platforms
Chetan Prasad,K. W. Park,M. Chahal,Inanc Meric,S. Novak,S. Ramey,P. Bai,Chang Hsu-Yu,N. L. Dias,Hafez Walid M,C.-H. Jan,Nidhi Nidhi,Olac-Vaw Roman W,Ramaswamy Rahul,Curtis Tsai +14 more
TL;DR: In this paper, the transistor reliability characterization of a 14nm System-on-Chip (SoC) node optimized for low power operation is described, and in-depth assessments of reliability and performance for Core and I/O devices are performed on Logic and SoC nodes, and clear trends with scaling are identified.
Patent
Monolithic integration of high voltage transistors & low voltage non-planar transistors
TL;DR: In this paper, a gate stack may be disposed over a high voltage channel region separating a pair of fins with each of the fins serving as part of a source/drain for the high voltage device.