Showing papers by "Shengdong Zhang published in 2017"

Solution‐Processed MoS2/Organolead Trihalide Perovskite Photodetectors

Abstract: Integration of organic/inorganic hybrid perovskites with metallic or semiconducting phases of 2D MoS2 nanosheets via solution processing is demonstrated. The results show that the collection of charge carriers is strongly dependent on the electronic properties of the 2D MoS2 with metallic MoS2 showing high responsivity and the semiconducting phase exhibiting high on/off ratios.

Efficient quantum dot light-emitting diodes with a Zn0.85Mg0.15O interfacial modification layer

Abstract: Efficient inverted quantum-dot (QD) light-emitting diodes (LEDs) are demonstrated by using 15% Mg doped ZnO (Zn0.85Mg0.15O) as an interfacial modification layer. By doping Mg into ZnO, the conduction band level, the density of oxygen vacancies and the conductivity of the ZnO can be tuned. To suppress excess electron injection, a 13 nm Zn0.85Mg0.15O interlayer with a relatively higher conduction band edge and lower conductivity is inserted between the ZnO electron transport layer and QD light-emitting layer, which improves the balance of charge injection and blocks the non-radiative pathway. Moreover, according to the electrical and optical studies of devices and materials, quenching sites at the ZnO surface are effectively reduced by Mg-doping. Therefore exciton quenching induced by ZnO nanoparticles is largely suppressed by capping ZnO with Zn0.85Mg0.15O. Consequently, the red QLEDs with a Zn0.85Mg0.15O interfacial modification layer exhibit superior performance with a maximum current efficiency of 18.69 cd A−1 and a peak external quantum efficiency of 13.57%, which are about 1.72- and 1.74-fold higher than 10.88 cd A−1 and 7.81% of the devices without Zn0.85Mg0.15O. Similar improvements are also achieved in green QLEDs. Our results indicate that Zn0.85Mg0.15O can serve as an effective interfacial modification layer for suppressing exciton quenching and improving the charge balance of the devices.

Attaining resistive switching characteristics and selector properties by varying forming polarities in a single HfO2-based RRAM device with a vanadium electrode

Abstract: This study proposes a method for a HfO2-based device to exhibit both resistive switching (RS) characteristics as resistive random access memory (RRAM) and selector characteristics by introducing vanadium (V) as the top electrode. This simple V/HfO2/TiN structure can demonstrate these two different properties depending on forming polarities. The RS mechanism is activated by a positive forming bias. In contrast, the selector property is induced by a negative forming bias. The material analyses firstly confirm the existence of V in the top electrode. Then the electrical measurements for the same V/HfO2/TiN structures but with different forming polarities were carried out to further investigate their DC sweeping characteristics to act as either a selector or RRAM device. Furthermore, reliability tests for both selector and RRAM devices were also conducted to confirm their switching stabilities. Finally, current fitting methods and temperature influence experiments were performed to investigate the carrier transport mechanisms. Finally, physical models were proposed to illustrate the selector property and RS mechanism for selector and RRAM devices, respectively. This simple device structure with its easy operating method accomplishes a significant advancement of devices combining both selector properties and RRAM for remarkable real applications in the near future.

Oxide Semiconductor Phototransistor with Organolead Trihalide Perovskite Light Absorber

Abstract: A hybrid phototransistor is developed with solution-processed organolead trihalide perovskite (MAPbI3) capping indium gallium zinc oxide (IGZO), which well fuses the properties of the two materials in sensitive photodetecting and high-mobility charge transporting, respectively. The MAPbI3-capped IGZO phototransistor demonstrates excellent responsivities of over 25 mA W−1 for lights with photon energies above the bandgap of perovskite light absorber. Besides the high sensitivity to light in both ultraviolet and visible regions, hybrid phototransistor maintains a fair on/off ratio of over 106 in the dark, and a field effect mobility of 12.9 cm2 V−1 s−1. The perovskite light absorber also obviates the long-standing problem for metal oxide phototransistor, the persistent photoconductivity behavior. Furthermore, fast transient response has been achieved by showing rise-time and fall-time within tens of milliseconds. The newly developed device opens variable optic-electric sensing applications for the integrated oxide–perovskite hybrid phototransistors.

Oxygen Interstitial Creation in a-IGZO Thin-Film Transistors Under Positive Gate-Bias Stress

Abstract: The electrical recovery behaviors of the amorphous InGaZnO thin-film transistors (a-IGZO TFTs) after positive gate-bias stress (PBS) are investigated. The TFTs show an evident sub-threshold swing (SS) degradation after the PBS removal when the channel layer is deposited at relatively high oxygen flow rates, although they exhibit a parallel positive shift in the transfer characteristics during the PBS. It is inferred that the SS degradation results from the oxygen interstitial defects created in the a-IGZO channel during the PBS, which are in the octahedral configuration and are usually more easily created in the oxygen-rich a-IGZO channel layer. They are electrically inactive during the PBS due to the “negative U” behavior and then become relaxed and electrically active during the recovery process, leading to the SS degradation during the recovery process.

Tunneling contact IGZO TFTs with reduced saturation voltages

Abstract: We report a tunneling contact indium-gallium-zinc oxide (IGZO) thin film transistor (TFT) with a graphene interlayer technique in this paper. A Schottky junction is realized between a metal and IGZO with a graphene interlayer, leading to a quantum tunneling of the TFT transport in saturation regions. This tunneling contact enables a significant reduction in the saturation drain voltage Vdsat compared to that of the thermionic emission TFTs, which is usually equal to the gate voltage minus their threshold voltages. Measured temperature independences of the subthreshold swing confirm a transition from the thermionic emission to quantum tunneling transports depending on the gate bias voltages in the proposed device. The tunneling contact TFTs with the graphene interlayer have implications to reduce the power consumptions of certain applications such as the active matrix OLED display.

Fully transparent high performance thin film transistors with bilayer ITO/Al-Sn-Zn-O channel structures fabricated on glass substrate

Abstract: In this work, fully transparent high performance double-channel indium-tin-oxide/Al–Sn–Zn–O thin-film transistors (ITO/ATZO TFTs) are successfully fabricated on glass by radio frequency (RF) magnetron sputtering. The ITO layer acts as the bottom channel layer to increase the channel carrier concentration. The top ATZO channel layer, which is deposited via high oxygen partial pressure in the sputtering process, is useful to control the minimum off-state current. After annealing, the ITO/ATZO TFT demonstrates outstanding electrical performances, including a high ON/OFF current ratio (Ion/Ioff) of 3.5 × 108, a steep threshold swing (SS) of 142.2 mV/decade, a superior saturation mobility (μsat) of 246.0 cm2/Vs, and a threshold voltage VT of 0.5 V. The operation mechanisms for double-channel structures are also clarified.

Solving the Scaling Issue of Increasing Forming Voltage in Resistive Random Access Memory Using High-k Spacer Structure

Abstract: In this study, the rising forming voltage issue during device cell scale-down in resistance random access memory (RRAM) is solved by introducing new high-permittivity (high-k) material as the side-wall spacer structure, unlike the normally used low-permittivity (low-k) material. Simulated electrical fields based on COMSOL Multiphysics software results suggest a RRAM device with a high-k spacer effectively confines the electric field. The effects of this confined electric field are notable, especially when the device cell is scaled down. The device fabrication process is modified to incorporate the high-k sidewall. Cross-sectional transmission electron microscopy imaging confirms the existence of SiO2 and HfO2 as the spacer structures in two different devices. Electrical measurements of forming voltages ranging from 1 to 0.16 µm2 are conducted to verify the effects. Statistical measurements confirm that the forming voltages of the devices with high-k material as sidewall do not increase with a reduction in device cell size. Moreover, reliability tests, including endurance and retention for the high-k sidewall device, also exhibit very stable resistance switching characteristics. As a result, the structure that is proposed successfully solves the forming voltage issues within small device cells in RRAM without any cost to device reliability.

Oxygen Adsorption Effect of Amorphous InGaZnO Thin-Film Transistors

Abstract: The effect of oxygen adsorption at the back channel of a-IGZO thin-film transistors (TFTs) is investigated. It is shown that for TFTs with the channel layer sputter-deposited at a high O2/Ar flow rate ratio ( $\text{R}_\text {O/Ar})$ , the threshold voltages in vacuum and O2 ambient do not show any difference; for devices fabricated at a low $\text{R}_{\text {O/Ar}}$ , the threshold voltages in vacuum are lower than those in O2. In addition, the devices in O2 show a more significant threshold voltage shift than those in vacuum do under a positive gate bias stress. The surface-state model is used to explain this observation. It is inferred that the oxygen adsorptions are physical and chemical, respectively, in the high- and low- $\text{R}_{\text {O/Ar}}$ cases, and the transition from physical to chemical adsorption occurs when a positive gate bias stress is applied.

Oxide Thin-Film Transistors With IMO and IGZO Stacked Active Layers for UV Detection

Abstract: Thin film transistors (TFTs) with amorphous InMgO (a-IMO) and InGaZnO (a-IGZO) stacked active layers are proposed to implement high-performance ultraviolet (UV) detectors. In this structure, the IGZO layer serves as the conductive layer and the IMO layer acts as the light absorption layer. The fabricated a-IGZO/a-IMO TFT shows comparable electrical characteristics to those of the conventional a-IGZO TFT as well as high UV photocurrent gain with good visible-blindness. In addition, the a-IGZO/a-IMO TFT-based sensor operates with stable and successive light detection. Thus, the a-IGZO/a-IMO TFT has been demonstrated to be able to act as both sensing and switching devices in the pixels of UV image sensors.

Effects of channel structure consisting of ZnO/Al2O3 multilayers on thin-film transistors fabricated by atomic layer deposition

Abstract: By applying a novel active layer comprising ZnO/Al2O3 multilayers, we have successfully fabricated fully transparent high-performance thin-film transistors (TFTs) with a bottom gate structure by atomic layer deposition (ALD) at low temperature. The effects of various ZnO/Al2O3 multilayers were studied to improve the morphological and electrical properties of the devices. We found that the ZnO/Al2O3 multilayers have a significant impact on the performance of the TFTs, and that the TFTs with the ZnO/15-cycle Al2O3/ZnO structure exhibit superior performance with a low threshold voltage (V TH) of 0.9 V, a high saturation mobility (μsat) of 145 cm2 V−1 s−1, a steep subthreshold swing (SS) of 162 mV/decade, and a high I on/I off ratio of 3.15 × 108. The enhanced electrical properties were explained by the improved crystalline nature of the channel layer and the passivation effect of the Al2O3 layer.

High-Performance Ti-Doped Zinc Oxide TFTs With Double-Layer Gate Dielectric Fabricated at Low Temperature

Abstract: In this study, titanium (Ti)-doped zinc oxide thin film transistors (TiZO TFTs) with a double-layer gate dielectric were successfully fabricated on glass at low temperature. A stacked 7 nm-thick Al 2 O 3 /180 nm-thick SiO 2 dielectric layer was used to improve the electrical performance of the TFTs, especially their leakage characteristics. Compared with the SiO 2 single dielectric, the devices with the double-layer Al 2 O 3 /SiO 2 dielectric layer showed optimized electrical properties. The saturation mobility (μ sat ), threshold voltage (v th ), subthreshold swing (SS), and I on /I off ratio obtained were 127 cm 2 V -1 s -1 , 1.09 V, 131 mV/decade, and 3.7 × 10 8 , respectively. Furthermore, the thickness of Al 2 O 3 in the double-layer gate dielectric was found to have considerable influence on the performance of the TiZO TFTs.

Nb Doped TiO2 Protected Back-channel-etched Amorphous Ingazno Thin Film Transistors

Abstract: A new back-channel-etched process for the fabrication of amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) is demonstrated, in which a conductive Nb doped TiO 2 (TNO) thin film is used to serve as protective layer for the a-IGZO active layer. It is shown that the TNO film provides the active layer with excellent protection even when the thickness is only 1 nm. With treatment by N 2 O plasma +200°C annealing, the conductive TNO can be converted into an insulator to serve as an in situ passivation layer. Besides, by the introduction of the TNO layer, the source-drain parasitic resistance of the BCE process fabricated TFTs is significantly reduced and the positive bias stress stability is improved as well.

Bi-layer Channel AZO/ZnO Thin Film Transistors Fabricated by Atomic Layer Deposition Technique

Abstract: This letter demonstrates bi-layer channel Al-doped ZnO/ZnO thin film transistors (AZO/ZnO TFTs) via atomic layer deposition process at a relatively low temperature. The effects of annealing in oxygen atmosphere at different temperatures have also been investigated. The ALD bi-layer channel AZO/ZnO TFTs annealed in dry O2 at 300 °C exhibit a low leakage current of 2.5 × 10−13A, I on/I off ratio of 1.4 × 107, subthreshold swing (SS) of 0.23 V/decade, and high transmittance. The enhanced performance obtained from the bi-layer channel AZO/ZnO TFT devices is explained by the inserted AZO front channel layer playing the role of the mobility booster.

Impact of repeated uniaxial mechanical strain on flexible a-IGZO thin film transistors with symmetric and asymmetric structures

Abstract: This letter investigates repeated uniaxial mechanical stress-induced degradation behavior in flexible amorphous In-Ga-Zn-O thin-film transistors (TFTs) of different geometric structures. Two types of via-contact structure TFTs are investigated: symmetrical and UI structure (TFTs with I- and U-shaped asymmetric electrodes). After repeated mechanical stress, I-V curves for the symmetrical structure show a significant negative threshold voltage (VT) shift, due to mechanical stress-induced oxygen vacancy generation. However, degradation in the UI structure TFTs after stress is a negative VT shift along with the parasitic transistor characteristic in the forward-operation mode, with this hump not evident in the reverse-operation mode. This asymmetrical degradation is clarified by the mechanical strain simulation of the UI TFTs.

The effect of device electrode geometry on performance after hot-carrier stress in amorphous In-Ga-Zn-O thin film transistors with different via-contact structures

Abstract: In this letter, the effects of hot carriers on amorphous In-Ga-Zn-O thin film transistors (TFTs) of different geometric structures were investigated Three types of via-contact structure TFTs are used in this experiment, defined as source-drain large (SD large), source-drain normal (SD normal), and fork-shaped After hot-carrier stress, the I-V curves of both SD normal and fork-shaped TFTs with U-shaped drains show a threshold voltage shift along with the parasitic transistor characteristic in the reverse-operation mode Asymmetrical degradation is exhibited in an ISE-TCAD simulation of the electric field, which shows the distribution of hot electrons injected into the etch-stop layer below the redundant drain electrode

A power-on-reset circuit with precisely triggered threshold voltages

Abstract: A power-on-reset (POR) circuit, which is an important block in mixed-signal integrated circuits, is used for the correct initialization of critical logic states in digital blocks of mixed-signal circuits. A POR circuit with precisely triggered threshold voltages is proposed. The circuit is designed in a 0.18 μm CMOS technology with a maximum 4 μA quiescent current. The output signal of the proposed circuit is also used to precisely detect whether the power supply is power-on or brown-out. The proposed POR circuit is insensitive to the power ramping time and tolerant to process variations. At typical corner, the proposed circuit reduces the quiescent current by more than 10x and layout area by 38% compared to the previously published designs.

Pixel device, driving method for pixel device and display device

Abstract: The invention relates to a pixel device, a driving method of the pixel device, and a display device. The pixel device includes a luminescent device, a driving transistor which is used to drive the luminescent device, a first transistor, and a boost memory unit, wherein a first pole of the driving transistor is coupled to a first common potential and a second pole of the driving transistor is coupled to an anode of the luminescent device; a control pole of the first transistor is used for receiving a first switching signal; a first pole of the first transistor is coupled to a control pole of the driving transistor, and a second pole of the first transistor is used for receiving data voltage information; the boost memory unit is coupled to the control pole and the second pole of the drivingtransistor, and includes a first capacitive element and a second capacitive element; the first capacitive element and the second capacitive element are used for storing threshold-voltage information and data voltage information of the driving transistor; and when the first transistor is cut-off, the voltage on the first capacitive element is used for driving the driving transistor. The technical scheme of the pixel device can improve the data voltage range so as to conveniently control the current of a luminescent element.

AZO Thin Film Transistor Performance Enhancement by Capping an Aluminum Layer

Abstract: Coplanar bottom-gate aluminum-zinc-oxide (AZO) thin film transistors (TFTs) with aluminum (Al) capping layers were fabricated in this work. The influences of the Al capping layer thickness and the post-annealing condition on the performance of the AZO-TFTswere investigated. Results show that the performance of the AZO-TFTs are enhanced significantly by introducing the Al capping layer on back channel, with saturation mobility increasing dramatically from 0.128 to 12.6 cm2/ $\text {V}\cdot \text {s}$ . The enhancement is ascribed to the diffusion of Al atoms into the AZO thin film and thus induced crystallization improvement.

Investigating degradation behaviors induced by mobile Cu ions under high temperature negative bias stress in a-InGaZnO thin film transistors

Abstract: This letter investigates the effect of negative bias temperature stress (NBTS) on amorphous InGaZnO4 thin film transistors with copper electrodes After 2000 s of NBTS, an abnormal subthreshold swing and on-current (Ion) degradation is observed The recovery of the Id-Vg curve after either annealing or positive bias temperature stress suggests that there are some native mobile copper ions in the active layer Both the existence of copper and the degradation mechanism can be confirmed by AC stress with different frequencies and by transmission electron microscope energy-dispersive X-ray spectroscopy analysis

Abnormal Recovery Phenomenon Induced by Hole Injection During Hot Carrier Degradation in SOI n-MOSFETs

Abstract: This letter investigates an abnormal recovery phenomenon induced by hole injection during hot carrier degradation in silicon-on-insulator n-type metal–oxide–semiconductor transistors. The method by which the hole injection induces the abnormal recovery behavior can be clarified by different hot carrier degradation (HCD) measurement sequences. According to this HCD result, the channel surface energy band is drawn down and the interface defect will be temporarily shielded, an effect caused by the trapped hole. Furthermore, results of different stress voltage experiments indicate that the amount of hole injection is determined by the electric field between the gate and drain.

Drain current model based on the Meyer-Neldel Rule for polycrystalline ZnO thin-film transistors at different temperatures

Abstract: Based on the Meyer-Neldel Rule (MNR), analytical drain current model is presented for the polycrystalline ZnO thin-film transistors at different temperatures. The MNR-based drain current model is developed from the surface-potential-based model considering the effective medium approximation (EMA). Applying the Meyer-Neldel Rule, the drain current model is developed. The model results are in agreement with the available experimental data at different temperatures.