T
T. H. Chan
Researcher at GlobalFoundries
Publications - 6
Citations - 97
T. H. Chan is an academic researcher from GlobalFoundries. The author has contributed to research in topics: Computer science & JEDEC memory standards. The author has an hindex of 2, co-authored 4 publications receiving 62 citations.
Papers
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Proceedings ArticleDOI
CMOS-embedded STT-MRAM arrays in 2x nm nodes for GP-MCU applications
Danny Pak-Chum Shum,Dimitri Houssameddine,S. T. Woo,Y. S. You,J. Wong,K. W. Wong,C. C. Wang,Kangho Lee,K. Yamane,Vinayak Bharat Naik,Chim Seng Seet,Taiebeh Tahmasebi,C. Hai,H. Yang,Naganivetha Thiyagarajah,R. Chao,J. W. Ting,N. L. Chung,T. Ling,T. H. Chan,S. Y. Siah,Rajesh R. Nair,Sarin A. Deshpande,Renu Whig,Kerry Joseph Nagel,Sanjeev Aggarwal,M. DeHerrera,J. Janesky,Ming-Wei Lin,H.-J. Chia,M. Hossain,H. Lu,Sumio Ikegawa,Frederick B. Mancoff,G. Shimon,Jon M. Slaughter,J. J. Sun,Michael Tran,Syed M. Alam,Thomas W. Andre +39 more
TL;DR: An unprecedented demonstration of a robust STT-MRAM technology designed in a 2x nm CMOS-embedded 40 Mb array with full array functionality, process uniformity and reliability, and 10 years data retention at 125C with extended endurance to ∼ 107 cycles is presented.
Proceedings ArticleDOI
22-nm FD-SOI Embedded MRAM with Full Solder Reflow Compatibility and Enhanced Magnetic Immunity
Kangho Lee,K. Yamane,Seung-Mo Noh,Vinayak Bharat Naik,H. Yang,S. H. Jang,J. Kwon,Behtash Behin-Aein,R. Chao,J. H. Lim,K. W. Gan,D. Zeng,Naganivetha Thiyagarajah,L. C. Goh,B. Liu,Eng Huat Toh,B. Jung,T. L. Wee,T. Ling,T. H. Chan,N. L. Chung,J. W. Ting,S. Lakshmipathi,J. S. Son,J. Hwang,L. Zhang,R. Low,Rishikesh Krishnan,T. Kitamura,Y. S. You,Chim Seng Seet,H. Cong,Danny Pak-Chum Shum,Jen Shuang Wong,S. T. Woo,J. Lam,E. Quek,A. See,S. Y. Siah +38 more
TL;DR: A fully functional embedded MRAM macro integrated into a 22-nm FD-SOI CMOS platform and showing intrinsic stand-by magnetic immunity of 1.4 kOe reveals that eMRAM is capable of serving a broad spectrum of eFlash applications at 22 nm or beyond.
Proceedings ArticleDOI
JEDEC-Qualified Highly Reliable 22nm FD-SOI Embedded MRAM For Low-Power Industrial-Grade, and Extended Performance Towards Automotive-Grade-1 Applications
Vinayak Bharat Naik,K. Yamane,Tae Young Lee,J. Kwon,R. Chao,J. H. Lim,N. L. Chung,Behtash Behin-Aein,L. Y. Hau,D. Zeng,Y. Otani,C. Chiang,Y. Huang,L. Pu,S. H. Jang,W. P. Neo,Hemant Dixit,S. K L. C. Goh,Eng Huat Toh,T. Ling,J. Hwang,J. W. Ting,R. Low,L. Zhang,C.G. Lee,N. Balasankaran,F. Tan,K. W. Gan,H. Yoon,G. Congedo,Johannes Mueller,B. Pfefferling,O. Kallensee,A. Vogel,V. Kriegerstein,T. Merbeth,Chim Seng Seet,S. Ong,Jeff J. Xu,Jen Shuang Wong,Y. S. You,S. T. Woo,T. H. Chan,E. Quek,Soh Yun Siah +44 more
TL;DR: In this paper, the authors demonstrate highly reliable and mass-production ready 22nm FD-SOI 40Mb embedded-MRAM for industrial-grade (-40~125°C) applications.
Proceedings ArticleDOI
Advanced MTJ Stack Engineering of STT-MRAM to Realize High Speed Applications
Tae Young Lee,K. Yamane,Y. Otani,D. Zeng,J. Kwon,J. H. Lim,Vinayak Bharat Naik,L. Y. Hau,R. Chao,N. L. Chung,T. Ling,S. H. Jang,L. C. Goh,J. Hwang,L. Zhang,R. Low,N. Balasankaran,F. Tan,J. W. Ting,J. Chang,Chim Seng Seet,S. Ong,Y. S. You,S. T. Woo,T. H. Chan,S. Y. Siah +25 more
TL;DR: In this paper, the authors demonstrate superior data retention of 1 month at 125°C with improved switching efficiency at 10 ns write time without back-hopping failure and showed an engineering pathway how advanced MTJ stack engineering can improve key device parameters.
Proceedings ArticleDOI
Extended MTJ TDDB Model, and Improved STT-MRAM Reliability With Reduced Circuit and Process Variabilities
Vinayak Bharat Naik,K. Yamane,J. Kwon,Behtash Behin-Aein,N. L. Chung,R. Chao,C. Chiang,Y. Huang,L. Pu,Yuichi Otani,S. H. Jang,N. Balasankaran,Wah-Peng Neo,Tan Yun Ling,J. W. Ting,Hongsik Yoon,Johannes Müller,B. Pfefferling,O. Kallensee,T. Merbeth,Chim Seng Seet,J. Wong,Y. S. You,Steven R. Soss,T. H. Chan,Soh Yun Siah +25 more
TL;DR: In this article , the authors present a reliable magnetic tunnel junction (MTJ) TDDB model using 40Mb 22FDX® STT-MRAM at sub-PPM failure rate.